DE69130626D1 - Verfahren zur Verwaltung einer Cache-Speicheranordnung - Google Patents

Verfahren zur Verwaltung einer Cache-Speicheranordnung

Info

Publication number
DE69130626D1
DE69130626D1 DE69130626T DE69130626T DE69130626D1 DE 69130626 D1 DE69130626 D1 DE 69130626D1 DE 69130626 T DE69130626 T DE 69130626T DE 69130626 T DE69130626 T DE 69130626T DE 69130626 D1 DE69130626 D1 DE 69130626D1
Authority
DE
Germany
Prior art keywords
managing
cache memory
memory arrangement
arrangement
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69130626T
Other languages
English (en)
Other versions
DE69130626T2 (de
Inventor
Edward C King
Forrest O Arnold
Jackson L Ellis
Robert B Moussavi
Pirmin L Weisser
Fulps V Vermeer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR International Inc
Original Assignee
NCR International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR International Inc filed Critical NCR International Inc
Publication of DE69130626D1 publication Critical patent/DE69130626D1/de
Application granted granted Critical
Publication of DE69130626T2 publication Critical patent/DE69130626T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0884—Parallel mode, e.g. in parallel with main memory or CPU

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69130626T 1990-08-06 1991-07-26 Verfahren zur Verwaltung einer Cache-Speicheranordnung Expired - Fee Related DE69130626T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/563,219 US5420994A (en) 1990-08-06 1990-08-06 Method for reading a multiple byte data element in a memory system with at least one cache and a main memory
US563219 1995-11-27

Publications (2)

Publication Number Publication Date
DE69130626D1 true DE69130626D1 (de) 1999-01-28
DE69130626T2 DE69130626T2 (de) 2006-02-23

Family

ID=24249595

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130626T Expired - Fee Related DE69130626T2 (de) 1990-08-06 1991-07-26 Verfahren zur Verwaltung einer Cache-Speicheranordnung

Country Status (4)

Country Link
US (1) US5420994A (de)
EP (1) EP0470739B1 (de)
JP (1) JPH04253240A (de)
DE (1) DE69130626T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5566324A (en) * 1992-12-24 1996-10-15 Ncr Corporation Computer apparatus including a main memory prefetch cache and method of operation thereof
US5623633A (en) * 1993-07-27 1997-04-22 Dell Usa, L.P. Cache-based computer system employing a snoop control circuit with write-back suppression
TW228580B (en) * 1993-10-01 1994-08-21 Ibm Information processing system and method of operation
EP0661638A1 (de) * 1993-12-28 1995-07-05 International Business Machines Corporation Verfahren und Einrichtung zur Datenübertragung in einem Rechner
US5553265A (en) * 1994-10-21 1996-09-03 International Business Machines Corporation Methods and system for merging data during cache checking and write-back cycles for memory reads and writes
JPH0916470A (ja) 1995-07-03 1997-01-17 Mitsubishi Electric Corp 半導体記憶装置
US5712970A (en) * 1995-09-28 1998-01-27 Emc Corporation Method and apparatus for reliably storing data to be written to a peripheral device subsystem using plural controllers
US5781916A (en) * 1996-03-25 1998-07-14 Motorola, Inc. Cache control circuitry and method therefor
US5860113A (en) * 1996-06-03 1999-01-12 Opti Inc. System for using a dirty bit with a cache memory
US5900016A (en) * 1997-04-02 1999-05-04 Opti Inc. System for using a cache memory with a write-back architecture
US6895475B2 (en) * 2002-09-30 2005-05-17 Analog Devices, Inc. Prefetch buffer method and apparatus
US8291174B2 (en) 2007-08-15 2012-10-16 Micron Technology, Inc. Memory device and method having on-board address protection system for facilitating interface with multiple processors, and computer system using same
US7822911B2 (en) * 2007-08-15 2010-10-26 Micron Technology, Inc. Memory device and method with on-board cache system for facilitating interface with multiple processors, and computer system using same
US8055852B2 (en) 2007-08-15 2011-11-08 Micron Technology, Inc. Memory device and method having on-board processing logic for facilitating interface with multiple processors, and computer system using same
US10026458B2 (en) 2010-10-21 2018-07-17 Micron Technology, Inc. Memories and methods for performing vector atomic memory operations with mask control and variable data length and data unit size

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4157586A (en) * 1977-05-05 1979-06-05 International Business Machines Corporation Technique for performing partial stores in store-thru memory configuration
US4323968A (en) * 1978-10-26 1982-04-06 International Business Machines Corporation Multilevel storage system having unitary control of data transfers
JPS58133696A (ja) * 1982-02-03 1983-08-09 Hitachi Ltd 記憶制御方式
US4680702A (en) * 1984-04-27 1987-07-14 Honeywell Information Systems Inc. Merge control apparatus for a store into cache of a data processing system
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
US5019971A (en) * 1987-04-13 1991-05-28 Prime Computer, Inc. High availability cache organization
US4926317A (en) * 1987-07-24 1990-05-15 Convex Computer Corporation Hierarchical memory system with logical cache, physical cache, and address translation unit for generating a sequence of physical addresses
JPH01163852A (ja) * 1987-10-02 1989-06-28 Computer Consoles Inc データ処理システム内のサブシステムおよびその動作方法
JPH0254383A (ja) * 1988-08-18 1990-02-23 Mitsubishi Electric Corp アレイプロセッサ
US5185875A (en) * 1989-01-27 1993-02-09 Digital Equipment Corporation Method and apparatus for reducing memory read latency in a shared memory system with multiple processors
US5155824A (en) * 1989-05-15 1992-10-13 Motorola, Inc. System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address
US5091851A (en) * 1989-07-19 1992-02-25 Hewlett-Packard Company Fast multiple-word accesses from a multi-way set-associative cache memory
US5073851A (en) * 1990-02-21 1991-12-17 Apple Computer, Inc. Apparatus and method for improved caching in a computer system

Also Published As

Publication number Publication date
EP0470739A1 (de) 1992-02-12
EP0470739B1 (de) 1998-12-16
DE69130626T2 (de) 2006-02-23
JPH04253240A (ja) 1992-09-09
US5420994A (en) 1995-05-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: V. BEZOLD & SOZIEN, 80799 MUENCHEN

8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee