DE69130342D1 - Mikroprozessor mit Funktion von Verzweigungsvorhersage - Google Patents

Mikroprozessor mit Funktion von Verzweigungsvorhersage

Info

Publication number
DE69130342D1
DE69130342D1 DE69130342T DE69130342T DE69130342D1 DE 69130342 D1 DE69130342 D1 DE 69130342D1 DE 69130342 T DE69130342 T DE 69130342T DE 69130342 T DE69130342 T DE 69130342T DE 69130342 D1 DE69130342 D1 DE 69130342D1
Authority
DE
Germany
Prior art keywords
microprocessor
branch prediction
prediction function
function
branch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69130342T
Other languages
English (en)
Other versions
DE69130342T2 (de
Inventor
Nariko Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69130342D1 publication Critical patent/DE69130342D1/de
Application granted granted Critical
Publication of DE69130342T2 publication Critical patent/DE69130342T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE69130342T 1990-05-22 1991-05-22 Mikroprozessor mit Funktion von Verzweigungsvorhersage Expired - Fee Related DE69130342T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2131812A JP2560889B2 (ja) 1990-05-22 1990-05-22 マイクロプロセッサ

Publications (2)

Publication Number Publication Date
DE69130342D1 true DE69130342D1 (de) 1998-11-19
DE69130342T2 DE69130342T2 (de) 1999-06-02

Family

ID=15066686

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130342T Expired - Fee Related DE69130342T2 (de) 1990-05-22 1991-05-22 Mikroprozessor mit Funktion von Verzweigungsvorhersage

Country Status (4)

Country Link
US (1) US5327536A (de)
EP (1) EP0458305B1 (de)
JP (1) JP2560889B2 (de)
DE (1) DE69130342T2 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3204323B2 (ja) * 1991-07-05 2001-09-04 エヌイーシーマイクロシステム株式会社 キャッシュメモリ内蔵マイクロプロセッサ
JP2744882B2 (ja) * 1993-01-15 1998-04-28 インターナショナル・ビジネス・マシーンズ・コーポレイション キューにより命令の実行を制御する装置及び方法
US5835967A (en) * 1993-10-18 1998-11-10 Cyrix Corporation Adjusting prefetch size based on source of prefetch address
TW253946B (en) * 1994-02-04 1995-08-11 Ibm Data processor with branch prediction and method of operation
US5673427A (en) * 1994-03-01 1997-09-30 Intel Corporation Packing valid micro operations received from a parallel decoder into adjacent locations of an output queue
JPH07326659A (ja) 1994-06-02 1995-12-12 Hitachi Ltd 半導体集積回路装置の製造方法
US5590358A (en) * 1994-09-16 1996-12-31 Philips Electronics North America Corporation Processor with word-aligned branch target in a byte-oriented instruction set
JPH08106387A (ja) * 1994-10-06 1996-04-23 Oki Electric Ind Co Ltd 命令プリフェッチ回路及びキャッシュ装置
US5734881A (en) * 1995-12-15 1998-03-31 Cyrix Corporation Detecting short branches in a prefetch buffer using target location information in a branch target cache
SE509499C2 (sv) * 1996-05-03 1999-02-01 Ericsson Telefon Ab L M Metod och anordning för hantering av villkorliga hopp vid instruktionsbehandling i en pipeline-arkitektur
US6341301B1 (en) * 1997-01-10 2002-01-22 Lsi Logic Corporation Exclusive multiple queue handling using a common processing algorithm
US6282663B1 (en) * 1997-01-22 2001-08-28 Intel Corporation Method and apparatus for performing power management by suppressing the speculative execution of instructions within a pipelined microprocessor
TW357318B (en) * 1997-03-18 1999-05-01 Ind Tech Res Inst Branching forecast and reading device for unspecified command length extra-purity pipeline processor
JPH10333908A (ja) * 1997-05-30 1998-12-18 Mitsubishi Electric Corp 分岐予測方法
US5881260A (en) * 1998-02-09 1999-03-09 Hewlett-Packard Company Method and apparatus for sequencing and decoding variable length instructions with an instruction boundary marker within each instruction
JP2002507789A (ja) * 1998-03-18 2002-03-12 クゥアルコム・インコーポレイテッド デジタル信号プロセッサ
US7149883B1 (en) 2000-03-30 2006-12-12 Intel Corporation Method and apparatus selectively to advance a write pointer for a queue based on the indicated validity or invalidity of an instruction stored within the queue
US20050278505A1 (en) 2004-05-19 2005-12-15 Lim Seow C Microprocessor architecture including zero impact predictive data pre-fetch mechanism for pipeline data memory
US20070074007A1 (en) 2005-09-28 2007-03-29 Arc International (Uk) Limited Parameterizable clip instruction and method of performing a clip operation using the same
US8935517B2 (en) * 2006-06-29 2015-01-13 Qualcomm Incorporated System and method for selectively managing a branch target address cache of a multiple-stage predictor

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5927935B2 (ja) * 1980-02-29 1984-07-09 株式会社日立製作所 情報処理装置
EP0109655B1 (de) * 1982-11-17 1991-07-24 Nec Corporation Anordnung zum Vorabholen von Befehlen mit Vorhersage einer Verzweigungszieladresse
JPS6051948A (ja) * 1983-08-31 1985-03-23 Hitachi Ltd 情報処理装置
US4894772A (en) * 1987-07-31 1990-01-16 Prime Computer, Inc. Method and apparatus for qualifying branch cache entries
US4943908A (en) * 1987-12-02 1990-07-24 International Business Machines Corporation Multiple branch analyzer for prefetching cache lines
JPH02306341A (ja) * 1989-02-03 1990-12-19 Nec Corp マイクロプロセッサ
US5093778A (en) * 1990-02-26 1992-03-03 Nexgen Microsystems Integrated single structure branch prediction cache

Also Published As

Publication number Publication date
US5327536A (en) 1994-07-05
JPH0425939A (ja) 1992-01-29
EP0458305B1 (de) 1998-10-14
EP0458305A3 (en) 1993-05-12
EP0458305A2 (de) 1991-11-27
JP2560889B2 (ja) 1996-12-04
DE69130342T2 (de) 1999-06-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee