DE69129913D1 - Datenprozessor mit aufgeschobenem Laden eines Cache-Speichers - Google Patents

Datenprozessor mit aufgeschobenem Laden eines Cache-Speichers

Info

Publication number
DE69129913D1
DE69129913D1 DE69129913T DE69129913T DE69129913D1 DE 69129913 D1 DE69129913 D1 DE 69129913D1 DE 69129913 T DE69129913 T DE 69129913T DE 69129913 T DE69129913 T DE 69129913T DE 69129913 D1 DE69129913 D1 DE 69129913D1
Authority
DE
Germany
Prior art keywords
cache memory
data processor
deferred loading
deferred
loading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69129913T
Other languages
English (en)
Other versions
DE69129913T2 (de
Inventor
Pamela S Laakso
Bradley Martin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE69129913D1 publication Critical patent/DE69129913D1/de
Publication of DE69129913T2 publication Critical patent/DE69129913T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
DE69129913T 1990-01-22 1991-01-10 Datenprozessor mit aufgeschobenem Laden eines Cache-Speichers Expired - Fee Related DE69129913T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/468,021 US5170476A (en) 1990-01-22 1990-01-22 Data processor having a deferred cache load

Publications (2)

Publication Number Publication Date
DE69129913D1 true DE69129913D1 (de) 1998-09-10
DE69129913T2 DE69129913T2 (de) 1999-03-04

Family

ID=23858121

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69129913T Expired - Fee Related DE69129913T2 (de) 1990-01-22 1991-01-10 Datenprozessor mit aufgeschobenem Laden eines Cache-Speichers

Country Status (5)

Country Link
US (1) US5170476A (de)
EP (1) EP0439025B1 (de)
JP (1) JP2870207B2 (de)
KR (1) KR910014818A (de)
DE (1) DE69129913T2 (de)

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US5247632A (en) * 1989-01-23 1993-09-21 Eastman Kodak Company Virtual memory management arrangement for addressing multi-dimensional arrays in a digital data processing system
US5335335A (en) * 1991-08-30 1994-08-02 Compaq Computer Corporation Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed
GB2260628A (en) * 1991-10-11 1993-04-21 Intel Corp Line buffer for cache memory
US5649154A (en) * 1992-02-27 1997-07-15 Hewlett-Packard Company Cache memory system having secondary cache integrated with primary cache for use with VLSI circuits
JP2737820B2 (ja) * 1992-09-24 1998-04-08 インターナショナル・ビジネス・マシーンズ・コーポレイション メモリアクセス方法およびシステム
JPH06222990A (ja) * 1992-10-16 1994-08-12 Fujitsu Ltd データ処理装置
GB2273181A (en) * 1992-12-02 1994-06-08 Ibm Cache/non-cache access control.
US5590368A (en) * 1993-03-31 1996-12-31 Intel Corporation Method and apparatus for dynamically expanding the pipeline of a microprocessor
JP2596712B2 (ja) * 1993-07-01 1997-04-02 インターナショナル・ビジネス・マシーンズ・コーポレイション 近接した分岐命令を含む命令の実行を管理するシステム及び方法
US5515521A (en) * 1994-02-08 1996-05-07 Meridian Semiconductor, Inc. Circuit and method for reducing delays associated with contention interference between code fetches and operand accesses of a microprocessor
US5692152A (en) * 1994-06-29 1997-11-25 Exponential Technology, Inc. Master-slave cache system with de-coupled data and tag pipelines and loop-back
US5551001A (en) * 1994-06-29 1996-08-27 Exponential Technology, Inc. Master-slave cache system for instruction and data cache memories
SE515718C2 (sv) * 1994-10-17 2001-10-01 Ericsson Telefon Ab L M System och förfarande för behandling av minnesdata samt kommunikationssystem
SE503506C2 (sv) * 1994-10-17 1996-06-24 Ericsson Telefon Ab L M System och förfarande för behandling av data samt kommunikationssystem med dylikt system
US5577228A (en) * 1994-12-08 1996-11-19 Sony Corporation Of Japan Digital circuit for performing multicycle addressing in a digital memory
US5586291A (en) * 1994-12-23 1996-12-17 Emc Corporation Disk controller with volatile and non-volatile cache memories
US5835949A (en) * 1994-12-27 1998-11-10 National Semiconductor Corporation Method of identifying and self-modifying code
US5809529A (en) * 1995-08-23 1998-09-15 International Business Machines Corporation Prefetching of committed instructions from a memory to an instruction cache
US5860150A (en) * 1995-10-06 1999-01-12 International Business Machines Corporation Instruction pre-fetching of a cache line within a processor
US6085291A (en) * 1995-11-06 2000-07-04 International Business Machines Corporation System and method for selectively controlling fetching and prefetching of data to a processor
US5835946A (en) * 1996-04-18 1998-11-10 International Business Machines Corporation High performance implementation of the load reserve instruction in a superscalar microprocessor that supports multi-level cache organizations
US5835947A (en) * 1996-05-31 1998-11-10 Sun Microsystems, Inc. Central processing unit and method for improving instruction cache miss latencies using an instruction buffer which conditionally stores additional addresses
US5983321A (en) * 1997-03-12 1999-11-09 Advanced Micro Devices, Inc. Cache holding register for receiving instruction packets and for providing the instruction packets to a predecode unit and instruction cache
US6122729A (en) * 1997-05-13 2000-09-19 Advanced Micro Devices, Inc. Prefetch buffer which stores a pointer indicating an initial predecode position
US6470444B1 (en) * 1999-06-16 2002-10-22 Intel Corporation Method and apparatus for dividing a store operation into pre-fetch and store micro-operations
US6898694B2 (en) * 2001-06-28 2005-05-24 Intel Corporation High instruction fetch bandwidth in multithread processor using temporary instruction cache to deliver portion of cache line in subsequent clock cycle
KR100546403B1 (ko) * 2004-02-19 2006-01-26 삼성전자주식회사 감소된 메모리 버스 점유 시간을 가지는 시리얼 플레쉬메모리 컨트롤러
US8055821B2 (en) * 2004-11-17 2011-11-08 International Business Machines Corporation Apparatus, system, and method for converting a synchronous interface into an asynchronous interface
WO2007099582A1 (ja) * 2006-02-28 2007-09-07 Fujitsu Limited プリフェッチ制御装置
US9086889B2 (en) * 2010-04-27 2015-07-21 Oracle International Corporation Reducing pipeline restart penalty
US10210090B1 (en) * 2017-10-12 2019-02-19 Texas Instruments Incorporated Servicing CPU demand requests with inflight prefetchs

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4701844A (en) * 1984-03-30 1987-10-20 Motorola Computer Systems, Inc. Dual cache for independent prefetch and execution units
DE3650782T2 (de) * 1985-02-22 2004-06-17 Intergraph Hardware Technologies Co., Las Vegas Anordnung von Cachespeicherverwaltungseinheiten
US4853846A (en) * 1986-07-29 1989-08-01 Intel Corporation Bus expander with logic for virtualizing single cache control into dual channels with separate directories and prefetch for different processors
US4888689A (en) * 1986-10-17 1989-12-19 Amdahl Corporation Apparatus and method for improving cache access throughput in pipelined processors
DE3862488D1 (de) * 1987-02-16 1991-05-29 Siemens Ag Verfahren zur steuerung des datenaustausches zwischen verarbeitungseinheiten und einem speichersystem mit cachespeicher in datenverarbeitungsanlagen, sowie ein entsprechend arbeitender cachespeicher.

Also Published As

Publication number Publication date
EP0439025B1 (de) 1998-08-05
EP0439025A2 (de) 1991-07-31
JPH04218835A (ja) 1992-08-10
DE69129913T2 (de) 1999-03-04
JP2870207B2 (ja) 1999-03-17
KR910014818A (ko) 1991-08-31
EP0439025A3 (en) 1992-09-09
US5170476A (en) 1992-12-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee