BR8903161A - Sistema de armazenamento em memoria cache e sistema de processamento de dados - Google Patents

Sistema de armazenamento em memoria cache e sistema de processamento de dados

Info

Publication number
BR8903161A
BR8903161A BR898903161A BR8903161A BR8903161A BR 8903161 A BR8903161 A BR 8903161A BR 898903161 A BR898903161 A BR 898903161A BR 8903161 A BR8903161 A BR 8903161A BR 8903161 A BR8903161 A BR 8903161A
Authority
BR
Brazil
Prior art keywords
data processing
cache memory
memory storage
processing system
storage system
Prior art date
Application number
BR898903161A
Other languages
English (en)
Inventor
Patrick Wayne Gallagher
Steven Lee Gregor
Stephen Michael Reeve
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR8903161A publication Critical patent/BR8903161A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
BR898903161A 1988-06-28 1989-06-28 Sistema de armazenamento em memoria cache e sistema de processamento de dados BR8903161A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US21256188A 1988-06-28 1988-06-28

Publications (1)

Publication Number Publication Date
BR8903161A true BR8903161A (pt) 1990-02-06

Family

ID=22791538

Family Applications (1)

Application Number Title Priority Date Filing Date
BR898903161A BR8903161A (pt) 1988-06-28 1989-06-28 Sistema de armazenamento em memoria cache e sistema de processamento de dados

Country Status (4)

Country Link
US (1) US5276848A (pt)
EP (1) EP0348628A3 (pt)
JP (1) JPH0239254A (pt)
BR (1) BR8903161A (pt)

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Also Published As

Publication number Publication date
EP0348628A2 (en) 1990-01-03
JPH0239254A (ja) 1990-02-08
US5276848A (en) 1994-01-04
EP0348628A3 (en) 1991-01-02

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