BR9203840A - Controlador de memoria e sistema de processamento de dados - Google Patents

Controlador de memoria e sistema de processamento de dados

Info

Publication number
BR9203840A
BR9203840A BR929203840A BR9203840A BR9203840A BR 9203840 A BR9203840 A BR 9203840A BR 929203840 A BR929203840 A BR 929203840A BR 9203840 A BR9203840 A BR 9203840A BR 9203840 A BR9203840 A BR 9203840A
Authority
BR
Brazil
Prior art keywords
data processing
processing system
memory controller
controller
memory
Prior art date
Application number
BR929203840A
Other languages
English (en)
Inventor
Norio Fujita
Mitsuhiro Gohda
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR9203840A publication Critical patent/BR9203840A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
BR929203840A 1991-10-11 1992-10-01 Controlador de memoria e sistema de processamento de dados BR9203840A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3290408A JPH0823843B2 (ja) 1991-10-11 1991-10-11 メモリ・コントローラ、及びデータ処理システム

Publications (1)

Publication Number Publication Date
BR9203840A true BR9203840A (pt) 1993-05-04

Family

ID=17755633

Family Applications (1)

Application Number Title Priority Date Filing Date
BR929203840A BR9203840A (pt) 1991-10-11 1992-10-01 Controlador de memoria e sistema de processamento de dados

Country Status (8)

Country Link
EP (1) EP0540198A1 (pt)
JP (1) JPH0823843B2 (pt)
KR (1) KR950014176B1 (pt)
CN (1) CN1040159C (pt)
BR (1) BR9203840A (pt)
CA (1) CA2079353A1 (pt)
SG (1) SG52203A1 (pt)
TW (1) TW200577B (pt)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5619471A (en) * 1995-06-06 1997-04-08 Apple Computer, Inc. Memory controller for both interleaved and non-interleaved memory
US6272600B1 (en) * 1996-11-15 2001-08-07 Hyundai Electronics America Memory request reordering in a data processing system
CN100405326C (zh) * 1997-07-24 2008-07-23 自由度半导体公司 访问存储器的方法以及数据处理系统
US6629219B1 (en) 2000-03-31 2003-09-30 Intel Corporation Method and apparatus for providing highly programmable memory mapping and improved interleaving
US7519693B2 (en) * 2004-11-18 2009-04-14 International Business Machines Corporation Apparatus, system, and method for integrating an enclosure
US7870351B2 (en) * 2007-11-15 2011-01-11 Micron Technology, Inc. System, apparatus, and method for modifying the order of memory accesses
JP2016218721A (ja) * 2015-05-20 2016-12-22 ソニー株式会社 メモリ制御回路およびメモリ制御方法
US10303398B2 (en) * 2017-10-26 2019-05-28 Advanced Micro Devices, Inc. Swizzling in 3D stacked memory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6149249A (ja) * 1984-08-17 1986-03-11 Fujitsu Ltd 記憶装置のインタリ−ブ制御方式
JPS61262862A (ja) * 1985-11-28 1986-11-20 Nec Corp 主記憶装置
US5341486A (en) * 1988-10-27 1994-08-23 Unisys Corporation Automatically variable memory interleaving system
TWM286903U (en) * 2005-01-25 2006-02-01 Shu-Shiung Guo Jewelry lamp

Also Published As

Publication number Publication date
TW200577B (pt) 1993-02-21
EP0540198A1 (en) 1993-05-05
CA2079353A1 (en) 1993-04-12
KR950014176B1 (ko) 1995-11-22
JPH05134923A (ja) 1993-06-01
SG52203A1 (en) 1998-09-28
CN1071771A (zh) 1993-05-05
CN1040159C (zh) 1998-10-07
JPH0823843B2 (ja) 1996-03-06
KR930008639A (ko) 1993-05-21

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Legal Events

Date Code Title Description
FA1 Application deemed withdrawn (art. 18(2))