DE69120737D1 - Schaltungen mit reduzierter Verzögerung für Schieberegisterabtastkette - Google Patents

Schaltungen mit reduzierter Verzögerung für Schieberegisterabtastkette

Info

Publication number
DE69120737D1
DE69120737D1 DE69120737T DE69120737T DE69120737D1 DE 69120737 D1 DE69120737 D1 DE 69120737D1 DE 69120737 T DE69120737 T DE 69120737T DE 69120737 T DE69120737 T DE 69120737T DE 69120737 D1 DE69120737 D1 DE 69120737D1
Authority
DE
Germany
Prior art keywords
shift register
scan chain
delay circuits
reduced delay
register scan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69120737T
Other languages
English (en)
Inventor
Paul Harold Bardell
William Howard Mcanney
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69120737D1 publication Critical patent/DE69120737D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/27—Built-in tests

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE69120737T 1990-08-01 1991-04-13 Schaltungen mit reduzierter Verzögerung für Schieberegisterabtastkette Expired - Lifetime DE69120737D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/561,399 US5150366A (en) 1990-08-01 1990-08-01 Reduced delay circuits for shift register latch scan strings

Publications (1)

Publication Number Publication Date
DE69120737D1 true DE69120737D1 (de) 1996-08-14

Family

ID=24241791

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69120737T Expired - Lifetime DE69120737D1 (de) 1990-08-01 1991-04-13 Schaltungen mit reduzierter Verzögerung für Schieberegisterabtastkette

Country Status (4)

Country Link
US (1) US5150366A (de)
EP (1) EP0469238B1 (de)
JP (1) JPH0772872B2 (de)
DE (1) DE69120737D1 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5377197A (en) * 1992-02-24 1994-12-27 University Of Illinois Method for automatically generating test vectors for digital integrated circuits
DE4318422A1 (de) * 1993-06-03 1994-12-08 Philips Patentverwaltung Integrierte Schaltung mit Registerstufen
US5592681A (en) * 1994-06-14 1997-01-07 Texas Instruments Incorporated Data processing with improved register bit structure
US5642362A (en) * 1994-07-20 1997-06-24 International Business Machines Corporation Scan-based delay tests having enhanced test vector pattern generation
US5640402A (en) * 1995-12-08 1997-06-17 International Business Machines Corporation Fast flush load of LSSD SRL chains
US5648973A (en) * 1996-02-06 1997-07-15 Ast Research, Inc. I/O toggle test method using JTAG
JP3363691B2 (ja) * 1996-03-13 2003-01-08 シャープ株式会社 半導体論理集積回路
US6044481A (en) * 1997-05-09 2000-03-28 Artisan Components, Inc. Programmable universal test interface for testing memories with different test methodologies
US5968192A (en) * 1997-05-09 1999-10-19 Artisan Components, Inc. Programmable universal test interface and method for making the same
US6125464A (en) * 1997-10-16 2000-09-26 Adaptec, Inc. High speed boundary scan design
US6314540B1 (en) 1999-04-12 2001-11-06 International Business Machines Corporation Partitioned pseudo-random logic test for improved manufacturability of semiconductor chips
US6327685B1 (en) * 1999-05-12 2001-12-04 International Business Machines Corporation Logic built-in self test
US6442723B1 (en) * 1999-05-12 2002-08-27 International Business Machines Corporation Logic built-in self test selective signature generation
US6976199B2 (en) * 2002-01-07 2005-12-13 International Business Machines Corporation AC LSSD/LBIST test coverage enhancement
US7032146B2 (en) * 2002-10-29 2006-04-18 International Business Machines Corporation Boundary scan apparatus and interconnect test method
US7484153B2 (en) * 2005-12-06 2009-01-27 Kabushiki Kaisha Toshiba Systems and methods for LBIST testing using isolatable scan chains
US20080082888A1 (en) * 2006-09-01 2008-04-03 Murray David W Measurement and calibration method for embedded diagnostic systems
US7908532B2 (en) * 2008-02-16 2011-03-15 International Business Machines Corporation Automated system and processing for expedient diagnosis of broken shift registers latch chains
US7908534B2 (en) * 2008-02-25 2011-03-15 International Business Machines Corporation Diagnosable general purpose test registers scan chain design
US7839155B2 (en) * 2008-12-15 2010-11-23 Texas Instruments Incorporated Methods and apparatus to analyze on-chip controlled integrated circuits

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5032783A (en) * 1985-10-23 1991-07-16 Texas Instruments Incorporated Test circuit and scan tested logic device with isolated data lines during testing
US4710933A (en) * 1985-10-23 1987-12-01 Texas Instruments Incorporated Parallel/serial scan system for testing logic circuits
US4718065A (en) * 1986-03-31 1988-01-05 Tandem Computers Incorporated In-line scan control apparatus for data processor testing
JPH0627776B2 (ja) * 1986-08-04 1994-04-13 三菱電機株式会社 半導体集積回路装置
JPS63256877A (ja) * 1987-04-14 1988-10-24 Mitsubishi Electric Corp テスト回路
US5043985A (en) * 1987-05-05 1991-08-27 Industrial Technology Research Institute Integrated circuit testing arrangement
US4860290A (en) * 1987-06-02 1989-08-22 Texas Instruments Incorporated Logic circuit having individually testable logic modules
US5043986A (en) * 1989-05-18 1991-08-27 At&T Bell Laboratories Method and integrated circuit adapted for partial scan testability

Also Published As

Publication number Publication date
EP0469238A3 (en) 1993-01-20
EP0469238B1 (de) 1996-07-10
JPH0772872B2 (ja) 1995-08-02
EP0469238A2 (de) 1992-02-05
JPH04233635A (ja) 1992-08-21
US5150366A (en) 1992-09-22

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Legal Events

Date Code Title Description
8332 No legal effect for de