DE69118945D1 - Verarbeitungsmethode mit einer Metall-Schiefablagerung - Google Patents

Verarbeitungsmethode mit einer Metall-Schiefablagerung

Info

Publication number
DE69118945D1
DE69118945D1 DE69118945T DE69118945T DE69118945D1 DE 69118945 D1 DE69118945 D1 DE 69118945D1 DE 69118945 T DE69118945 T DE 69118945T DE 69118945 T DE69118945 T DE 69118945T DE 69118945 D1 DE69118945 D1 DE 69118945D1
Authority
DE
Germany
Prior art keywords
processing method
metal deposit
slanted metal
slanted
deposit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69118945T
Other languages
English (en)
Other versions
DE69118945T2 (de
Inventor
Yoshikazu Nakagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Application granted granted Critical
Publication of DE69118945D1 publication Critical patent/DE69118945D1/de
Publication of DE69118945T2 publication Critical patent/DE69118945T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Drying Of Semiconductors (AREA)
DE69118945T 1990-02-23 1991-01-30 Verarbeitungsmethode mit einer Metall-Schiefablagerung Expired - Fee Related DE69118945T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2042857A JPH03245527A (ja) 1990-02-23 1990-02-23 微細加工方法

Publications (2)

Publication Number Publication Date
DE69118945D1 true DE69118945D1 (de) 1996-05-30
DE69118945T2 DE69118945T2 (de) 1997-01-16

Family

ID=12647697

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69118945T Expired - Fee Related DE69118945T2 (de) 1990-02-23 1991-01-30 Verarbeitungsmethode mit einer Metall-Schiefablagerung

Country Status (4)

Country Link
US (1) US5126288A (de)
EP (1) EP0443348B1 (de)
JP (1) JPH03245527A (de)
DE (1) DE69118945T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05206025A (ja) * 1992-01-27 1993-08-13 Rohm Co Ltd 微細加工方法
EP0569745A1 (de) * 1992-05-14 1993-11-18 Siemens Aktiengesellschaft Verfahren zur Herstellung eines Feldeffekttransistoren mit asymmetrischer Gate-Struktur
JP3412037B2 (ja) * 1996-03-12 2003-06-03 株式会社デンソー 微細加工方法
JP3003608B2 (ja) * 1997-01-23 2000-01-31 日本電気株式会社 半導体装置の製造方法
US6958295B1 (en) * 1998-01-20 2005-10-25 Tegal Corporation Method for using a hard mask for critical dimension growth containment
US6037005A (en) * 1998-05-12 2000-03-14 3M Innovative Properties Company Display substrate electrodes with auxiliary metal layers for enhanced conductivity
US6194268B1 (en) 1998-10-30 2001-02-27 International Business Machines Corporation Printing sublithographic images using a shadow mandrel and off-axis exposure
US6578264B1 (en) 1999-06-04 2003-06-17 Cascade Microtech, Inc. Method for constructing a membrane probe using a depression
DE10027932C2 (de) * 2000-05-31 2003-10-02 Infineon Technologies Ag Verfahren zur Bildung eines Kontaktlochs in einer Isolierschicht eines elektronischen oder mikroelektronischen Bauelements
JP2002026034A (ja) * 2000-07-05 2002-01-25 Oki Electric Ind Co Ltd 半導体装置の製造方法
DE10115912A1 (de) * 2001-03-30 2002-10-17 Infineon Technologies Ag Verfahren zur Herstellung einer Halbleiteranordnung und Verwendung einer Ionenstrahlanlage zur Durchführung des Verfahrens
PT1355359E (pt) * 2002-03-19 2007-07-13 Scheuten Glasgroep Bv Conexão em série de auto-ajuste de camadas finas e grossas e processo para o fabrico.
EP1357602A1 (de) * 2002-03-19 2003-10-29 Scheuten Glasgroep Selbstjustierende Serienverschaltung von Dünnschichten und Verfahren zur Herstellung
WO2009029302A2 (en) * 2007-05-08 2009-03-05 University Of Washington Shadow edge lithography for nanoscale patterning and manufacturing
US8476168B2 (en) * 2011-01-26 2013-07-02 International Business Machines Corporation Non-conformal hardmask deposition for through silicon etch
US10927450B2 (en) * 2018-12-19 2021-02-23 Applied Materials, Inc. Methods and apparatus for patterning substrates using asymmetric physical vapor deposition

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3103615A1 (de) * 1981-02-03 1982-09-09 Siemens AG, 1000 Berlin und 8000 München Verfahren zur erzeugung von extremen feinstrukturen
US4629686A (en) * 1982-02-19 1986-12-16 Endotronics, Inc. Apparatus for delivering a controlled dosage of a chemical substance
JPS58153349A (ja) * 1982-03-08 1983-09-12 Nec Corp 半導体装置の製造方法
US4525919A (en) * 1982-06-16 1985-07-02 Raytheon Company Forming sub-micron electrodes by oblique deposition
JPS6054453A (ja) * 1983-09-05 1985-03-28 Oki Electric Ind Co Ltd 半導体集積回路装置の製造方法
JPS60133739A (ja) * 1983-12-21 1985-07-16 Fujitsu Ltd 半導体装置の製造方法
US4618510A (en) * 1984-09-05 1986-10-21 Hewlett Packard Company Pre-passivated sub-micrometer gate electrodes for MESFET devices
JPS61198725A (ja) * 1985-02-28 1986-09-03 Matsushita Electric Ind Co Ltd 微細加工法
US4849376A (en) * 1987-01-12 1989-07-18 Itt A Division Of Itt Corporation Gallium Arsenide Technology Center Self-aligned refractory gate process with self-limiting undercut of an implant mask
US4903089A (en) * 1988-02-02 1990-02-20 Massachusetts Institute Of Technology Vertical transistor device fabricated with semiconductor regrowth

Also Published As

Publication number Publication date
JPH03245527A (ja) 1991-11-01
DE69118945T2 (de) 1997-01-16
EP0443348A3 (en) 1992-01-08
US5126288A (en) 1992-06-30
EP0443348A2 (de) 1991-08-28
EP0443348B1 (de) 1996-04-24

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Legal Events

Date Code Title Description
8332 No legal effect for de
8370 Indication of lapse of patent is to be deleted
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee