DE69033602T2 - Verfahren zur Herstellung von Isolationsstrukturen mit variabler Breite - Google Patents

Verfahren zur Herstellung von Isolationsstrukturen mit variabler Breite

Info

Publication number
DE69033602T2
DE69033602T2 DE69033602T DE69033602T DE69033602T2 DE 69033602 T2 DE69033602 T2 DE 69033602T2 DE 69033602 T DE69033602 T DE 69033602T DE 69033602 T DE69033602 T DE 69033602T DE 69033602 T2 DE69033602 T2 DE 69033602T2
Authority
DE
Germany
Prior art keywords
production
isolation structures
variable width
variable
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69033602T
Other languages
English (en)
Other versions
DE69033602D1 (de
Inventor
Michael S Liu
Roger L Roisen
Curtis H Rahn
John B Straight
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE69033602D1 publication Critical patent/DE69033602D1/de
Application granted granted Critical
Publication of DE69033602T2 publication Critical patent/DE69033602T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
DE69033602T 1989-06-30 1990-06-26 Verfahren zur Herstellung von Isolationsstrukturen mit variabler Breite Expired - Fee Related DE69033602T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/374,960 US5017999A (en) 1989-06-30 1989-06-30 Method for forming variable width isolation structures

Publications (2)

Publication Number Publication Date
DE69033602D1 DE69033602D1 (de) 2000-09-14
DE69033602T2 true DE69033602T2 (de) 2001-04-12

Family

ID=23478918

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69033602T Expired - Fee Related DE69033602T2 (de) 1989-06-30 1990-06-26 Verfahren zur Herstellung von Isolationsstrukturen mit variabler Breite

Country Status (5)

Country Link
US (1) US5017999A (de)
EP (1) EP0405923B1 (de)
JP (1) JP2775194B2 (de)
CA (1) CA2015891C (de)
DE (1) DE69033602T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5223736A (en) * 1989-09-27 1993-06-29 Texas Instruments Incorporated Trench isolation process with reduced topography
JP3144817B2 (ja) * 1990-03-23 2001-03-12 株式会社東芝 半導体装置
JP2551203B2 (ja) * 1990-06-05 1996-11-06 三菱電機株式会社 半導体装置
US5382541A (en) * 1992-08-26 1995-01-17 Harris Corporation Method for forming recessed oxide isolation containing deep and shallow trenches
EP0635884A1 (de) * 1993-07-13 1995-01-25 Siemens Aktiengesellschaft Verfahren zur Herstellung eines Grabens in einem Substrat und dessen Verwendung in der Smart-Power-Technologie
US5366925A (en) * 1993-09-27 1994-11-22 United Microelectronics Corporation Local oxidation of silicon by using aluminum spiking technology
US5372968A (en) * 1993-09-27 1994-12-13 United Microelectronics Corporation Planarized local oxidation by trench-around technology
US5294562A (en) * 1993-09-27 1994-03-15 United Microelectronics Corporation Trench isolation with global planarization using flood exposure
US5308786A (en) * 1993-09-27 1994-05-03 United Microelectronics Corporation Trench isolation for both large and small areas by means of silicon nodules after metal etching
US5672242A (en) * 1996-01-31 1997-09-30 Integrated Device Technology, Inc. High selectivity nitride to oxide etch process
KR100242466B1 (ko) * 1996-06-27 2000-02-01 김영환 채널스탑이온주입에 따른 좁은폭효과 방지를 위한 소자분리 구조를 갖는 반도체장치 및 그 제조방법
EP1641045A3 (de) 2002-11-12 2006-06-07 Micron Technology, Inc. Geerdete Gateelektrode und Isolationstechniken für reduzierte Dunkelströme im CMOS-Bildsensoren
KR200405882Y1 (ko) * 2005-10-21 2006-01-11 김대영 핸드폰 보호 필름 구조
US8642419B2 (en) 2012-02-20 2014-02-04 Globalfoundries Inc. Methods of forming isolation structures for semiconductor devices
US9330959B2 (en) * 2014-04-13 2016-05-03 Texas Instruments Incorporated Isolated semiconductor layer in bulk wafer by localized silicon epitaxial seed formation
US11387319B2 (en) 2019-09-11 2022-07-12 International Business Machines Corporation Nanosheet transistor device with bottom isolation

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4139401A (en) * 1963-12-04 1979-02-13 Rockwell International Corporation Method of producing electrically isolated semiconductor devices on common crystalline substrate
US3717514A (en) * 1970-10-06 1973-02-20 Motorola Inc Single crystal silicon contact for integrated circuits and method for making same
US4470062A (en) * 1979-08-31 1984-09-04 Hitachi, Ltd. Semiconductor device having isolation regions
US4487639A (en) * 1980-09-26 1984-12-11 Texas Instruments Incorporated Localized epitaxy for VLSI devices
EP0075589B1 (de) * 1981-03-27 1987-01-14 Western Electric Company, Incorporated Gate-gesteuerter diodeschalter
US4508579A (en) * 1981-03-30 1985-04-02 International Business Machines Corporation Lateral device structures using self-aligned fabrication techniques
US4454646A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
US4412868A (en) * 1981-12-23 1983-11-01 General Electric Company Method of making integrated circuits utilizing ion implantation and selective epitaxial growth
US4502913A (en) * 1982-06-30 1985-03-05 International Business Machines Corporation Total dielectric isolation for integrated circuits
US4473598A (en) * 1982-06-30 1984-09-25 International Business Machines Corporation Method of filling trenches with silicon and structures
US4400411A (en) * 1982-07-19 1983-08-23 The United States Of America As Represented By The Secretary Of The Air Force Technique of silicon epitaxial refill
JPS5939711A (ja) * 1982-08-26 1984-03-05 Ushio Inc ウエハ−上のアモルファスシリコンもしくは多結晶シリコンをエピタキシアル成長させる方法
US4507158A (en) * 1983-08-12 1985-03-26 Hewlett-Packard Co. Trench isolated transistors in semiconductor films
KR900001267B1 (ko) * 1983-11-30 1990-03-05 후지쓰 가부시끼가이샤 Soi형 반도체 장치의 제조방법
JPS60136361A (ja) * 1983-12-26 1985-07-19 Hitachi Ltd 半導体装置
US4547793A (en) * 1983-12-27 1985-10-15 International Business Machines Corporation Trench-defined semiconductor structure
US4688069A (en) * 1984-03-22 1987-08-18 International Business Machines Corporation Isolation for high density integrated circuits
JPS60207363A (ja) * 1984-03-31 1985-10-18 Toshiba Corp 半導体装置
JPS60244036A (ja) * 1984-05-18 1985-12-03 Hitachi Ltd 半導体装置とその製造方法
FR2566179B1 (fr) * 1984-06-14 1986-08-22 Commissariat Energie Atomique Procede d'autopositionnement d'un oxyde de champ localise par rapport a une tranchee d'isolement
US4680614A (en) * 1984-06-25 1987-07-14 Beyer Klaus D Planar void free isolation structure
US4526631A (en) * 1984-06-25 1985-07-02 International Business Machines Corporation Method for forming a void free isolation pattern utilizing etch and refill techniques
US4689656A (en) * 1984-06-25 1987-08-25 International Business Machines Corporation Method for forming a void free isolation pattern and resulting structure
US4528047A (en) * 1984-06-25 1985-07-09 International Business Machines Corporation Method for forming a void free isolation structure utilizing etch and refill techniques
US4551394A (en) * 1984-11-26 1985-11-05 Honeywell Inc. Integrated three-dimensional localized epitaxial growth of Si with localized overgrowth of GaAs
US4592792A (en) * 1985-01-23 1986-06-03 Rca Corporation Method for forming uniformly thick selective epitaxial silicon
JPS61230333A (ja) * 1985-04-05 1986-10-14 Nec Corp 集積回路
JPS61263067A (ja) * 1985-05-15 1986-11-21 Kobe Steel Ltd 内部リフオ−ミング式燃料電池のための複合化構成要素
JPS6365641A (ja) * 1986-09-05 1988-03-24 Nec Corp 半導体集積回路
US4819052A (en) * 1986-12-22 1989-04-04 Texas Instruments Incorporated Merged bipolar/CMOS technology using electrically active trench
JPS6432672A (en) * 1987-07-29 1989-02-02 Hitachi Ltd Semiconductor device
US4791073A (en) * 1987-11-17 1988-12-13 Motorola Inc. Trench isolation method for semiconductor devices
US4908328A (en) * 1989-06-06 1990-03-13 National Semiconductor Corporation High voltage power IC process

Also Published As

Publication number Publication date
CA2015891A1 (en) 1990-12-31
JPH0338857A (ja) 1991-02-19
EP0405923A3 (en) 1992-09-30
CA2015891C (en) 2000-06-06
EP0405923B1 (de) 2000-08-09
DE69033602D1 (de) 2000-09-14
JP2775194B2 (ja) 1998-07-16
EP0405923A2 (de) 1991-01-02
US5017999A (en) 1991-05-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee