JPS6432672A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6432672A
JPS6432672A JP62187523A JP18752387A JPS6432672A JP S6432672 A JPS6432672 A JP S6432672A JP 62187523 A JP62187523 A JP 62187523A JP 18752387 A JP18752387 A JP 18752387A JP S6432672 A JPS6432672 A JP S6432672A
Authority
JP
Japan
Prior art keywords
substrate
layer
electrons
impurity layer
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62187523A
Other languages
Japanese (ja)
Inventor
Yukihiro Onouchi
Yoichi Tamaoki
Toru Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62187523A priority Critical patent/JPS6432672A/en
Publication of JPS6432672A publication Critical patent/JPS6432672A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/10—DRAM devices comprising bipolar components

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To improve an effect for preventing the malfunction of a circuit, and to enhance the degree of integration by applying reverse bias to an impurity layer through polycrystalline silicon from an electrode and forming a depletion layer between the impurity layer and a substrate. CONSTITUTION:Voltage is applied to an impurity layer 2 up to reverse bias to a substrate 1 through polycrystalline silicon 3 from an electrode, and a depletion layer 9 is shaped between the impurity layer 2 and the substrate 1. When electrons and holes shaped by the projection of alpha-rays from the outside move in the substrate 1 and approach to an element, electrons are sucked into the impurity layer 2 when the substrate 1 takes a P-type and holes into the layer 2 when the substrate takes an N-type by the potential gradient of the depletion layer 9, and electrons and holes flow out to an external power through polycrystalline silicon 3. Accordingly, electrons and holes reaching to an element region are decreased, thus reducing the fluctuation of potential in a circuit by the inflow of charges.
JP62187523A 1987-07-29 1987-07-29 Semiconductor device Pending JPS6432672A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62187523A JPS6432672A (en) 1987-07-29 1987-07-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62187523A JPS6432672A (en) 1987-07-29 1987-07-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6432672A true JPS6432672A (en) 1989-02-02

Family

ID=16207571

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62187523A Pending JPS6432672A (en) 1987-07-29 1987-07-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6432672A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0405923A2 (en) * 1989-06-30 1991-01-02 Samsung Electronics Co., Ltd. Method for forming variable width isolation structures
JPH03187257A (en) * 1989-12-16 1991-08-15 Takehide Shirato Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0405923A2 (en) * 1989-06-30 1991-01-02 Samsung Electronics Co., Ltd. Method for forming variable width isolation structures
EP0405923B1 (en) * 1989-06-30 2000-08-09 Samsung Electronics Co., Ltd. Method for forming variable width isolation structures
JPH03187257A (en) * 1989-12-16 1991-08-15 Takehide Shirato Semiconductor device

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