DE69032851T2 - Integrierte Schaltung vom Josephson-Typ mit einer Ausgangsschnittstelle, welche die Ausgangsdaten mit reduzierter Taktfrequenz liefern kann - Google Patents

Integrierte Schaltung vom Josephson-Typ mit einer Ausgangsschnittstelle, welche die Ausgangsdaten mit reduzierter Taktfrequenz liefern kann

Info

Publication number
DE69032851T2
DE69032851T2 DE69032851T DE69032851T DE69032851T2 DE 69032851 T2 DE69032851 T2 DE 69032851T2 DE 69032851 T DE69032851 T DE 69032851T DE 69032851 T DE69032851 T DE 69032851T DE 69032851 T2 DE69032851 T2 DE 69032851T2
Authority
DE
Germany
Prior art keywords
deliver
integrated circuit
clock frequency
reduced clock
output data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69032851T
Other languages
English (en)
Other versions
DE69032851D1 (de
Inventor
Seigo Kotani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69032851D1 publication Critical patent/DE69032851D1/de
Application granted granted Critical
Publication of DE69032851T2 publication Critical patent/DE69032851T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/825—Apparatus per se, device per se, or process of making or operating same
    • Y10S505/829—Electrical computer or data processing system
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/825—Apparatus per se, device per se, or process of making or operating same
    • Y10S505/856—Electrical transmission or interconnection system
    • Y10S505/857—Nonlinear solid-state device system or circuit
    • Y10S505/858—Digital logic
    • Y10S505/859—Function of and, or, nand, nor or not

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Logic Circuits (AREA)
DE69032851T 1989-09-29 1990-09-25 Integrierte Schaltung vom Josephson-Typ mit einer Ausgangsschnittstelle, welche die Ausgangsdaten mit reduzierter Taktfrequenz liefern kann Expired - Fee Related DE69032851T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25586989 1989-09-29

Publications (2)

Publication Number Publication Date
DE69032851D1 DE69032851D1 (de) 1999-02-04
DE69032851T2 true DE69032851T2 (de) 1999-05-12

Family

ID=17284708

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69032851T Expired - Fee Related DE69032851T2 (de) 1989-09-29 1990-09-25 Integrierte Schaltung vom Josephson-Typ mit einer Ausgangsschnittstelle, welche die Ausgangsdaten mit reduzierter Taktfrequenz liefern kann

Country Status (5)

Country Link
US (1) US5126598A (de)
EP (1) EP0420579B1 (de)
JP (1) JP3053419B2 (de)
KR (1) KR930010016B1 (de)
DE (1) DE69032851T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5315180A (en) * 1992-02-13 1994-05-24 Fujitsu Limited Synchronizing interface circuit between semiconductor element circuit and a Josephson junction element circuit
US5939895A (en) * 1997-06-13 1999-08-17 Trw Inc. Frozen wave high speed receiver
US6242939B1 (en) * 1999-03-05 2001-06-05 Nec Corporation Superconducting circuit having superconductive circuit device of voltage-type logic and superconductive circuit device of fluxoid-type logic device selectively used therein
US7274705B2 (en) * 2000-10-03 2007-09-25 Broadcom Corporation Method and apparatus for reducing clock speed and power consumption
JP3920830B2 (ja) 2003-09-19 2007-05-30 三洋電機株式会社 インターフェース回路、データ処理回路、データ処理システム、集積回路
EP1927004B1 (de) * 2005-09-08 2010-12-15 Nxp B.V. Scanprüfverfahren
KR100684934B1 (ko) * 2005-11-28 2007-02-22 한국표준과학연구원 다중 주파수의 마이크로파 구동을 이용하여 프로그램가능한 조셉슨 전압 표준장치
US8571614B1 (en) 2009-10-12 2013-10-29 Hypres, Inc. Low-power biasing networks for superconducting integrated circuits
US9520180B1 (en) 2014-03-11 2016-12-13 Hypres, Inc. System and method for cryogenic hybrid technology computing and memory
US10222416B1 (en) 2015-04-14 2019-03-05 Hypres, Inc. System and method for array diagnostics in superconducting integrated circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4367420A (en) * 1980-06-02 1983-01-04 Thompson Foss Incorporated Dynamic logic circuits operating in a differential mode for array processing
DE3118621A1 (de) * 1981-05-11 1982-11-25 Siemens AG, 1000 Berlin und 8000 München Anordnung zum auslesen eindeutiger informationen aus einem digitalen schaltwerk bei zueinander asynchronen steuersignalen fuer das weiterschalten des schaltwerks und das uebernehmen der informationen
US4501975A (en) * 1982-02-16 1985-02-26 Sperry Corporation Josephson junction latch circuit
US4633439A (en) * 1982-07-21 1986-12-30 Hitachi, Ltd. Superconducting read-only memories or programable logic arrays having the same
JPH07111728B2 (ja) * 1988-03-23 1995-11-29 沖電気工業株式会社 帳票読み取り処理装置

Also Published As

Publication number Publication date
EP0420579A2 (de) 1991-04-03
EP0420579A3 (en) 1992-09-23
KR910007143A (ko) 1991-04-30
JPH03189995A (ja) 1991-08-19
DE69032851D1 (de) 1999-02-04
KR930010016B1 (ko) 1993-10-14
JP3053419B2 (ja) 2000-06-19
EP0420579B1 (de) 1998-12-23
US5126598A (en) 1992-06-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee