DE69031143D1 - Methode zum Ätzen von Polyimiden und resultierenden passivierten Strukturen - Google Patents

Methode zum Ätzen von Polyimiden und resultierenden passivierten Strukturen

Info

Publication number
DE69031143D1
DE69031143D1 DE69031143T DE69031143T DE69031143D1 DE 69031143 D1 DE69031143 D1 DE 69031143D1 DE 69031143 T DE69031143 T DE 69031143T DE 69031143 T DE69031143 T DE 69031143T DE 69031143 D1 DE69031143 D1 DE 69031143D1
Authority
DE
Germany
Prior art keywords
resulting passivated
structures
etching polyimides
polyimides
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69031143T
Other languages
English (en)
Other versions
DE69031143T2 (de
Inventor
Thomas E Kindl
Paul G Rickerl
David J Russel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69031143D1 publication Critical patent/DE69031143D1/de
Publication of DE69031143T2 publication Critical patent/DE69031143T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/002—Etching of the substrate by chemical or physical means by liquid chemical etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0166—Polymeric layer used for special processing, e.g. resist for etching insulating material or photoresist used as a mask during plasma etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0779—Treatments involving liquids, e.g. plating, rinsing characterised by the specific liquids involved
    • H05K2203/0786—Using an aqueous solution, e.g. for cleaning or during drilling of holes
    • H05K2203/0793—Aqueous alkaline solution, e.g. for cleaning or etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4092—Integral conductive tabs, i.e. conductive parts partly detached from the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Laminated Bodies (AREA)
DE69031143T 1989-04-26 1990-02-23 Methode zum Ätzen von Polyimiden und resultierenden passivierten Strukturen Expired - Lifetime DE69031143T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/343,217 US4911786A (en) 1989-04-26 1989-04-26 Method of etching polyimides and resulting passivation structure

Publications (2)

Publication Number Publication Date
DE69031143D1 true DE69031143D1 (de) 1997-09-04
DE69031143T2 DE69031143T2 (de) 1998-02-12

Family

ID=23345176

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69031143T Expired - Lifetime DE69031143T2 (de) 1989-04-26 1990-02-23 Methode zum Ätzen von Polyimiden und resultierenden passivierten Strukturen

Country Status (4)

Country Link
US (1) US4911786A (de)
EP (1) EP0394638B1 (de)
JP (1) JPH02302053A (de)
DE (1) DE69031143T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5300402A (en) * 1988-12-30 1994-04-05 International Business Machines Corporation Composition for photo imaging
US6210862B1 (en) 1989-03-03 2001-04-03 International Business Machines Corporation Composition for photoimaging
US5217849A (en) * 1989-08-28 1993-06-08 Sumitomo Metal Mining Company Limited Process for making a two-layer film carrier
US5066360A (en) * 1990-09-24 1991-11-19 International Business Machines Corp. Pad printing of resist over via holes
US5227008A (en) * 1992-01-23 1993-07-13 Minnesota Mining And Manufacturing Company Method for making flexible circuits
US5334487A (en) * 1992-07-23 1994-08-02 International Business Machines Corporation Method for forming a patterned layer on a substrate
US5350487A (en) * 1993-05-03 1994-09-27 Ameen Thomas J Method of etching polyimide
US5960306A (en) * 1995-12-15 1999-09-28 Motorola, Inc. Process for forming a semiconductor device
US5993945A (en) * 1996-05-30 1999-11-30 International Business Machines Corporation Process for high resolution photoimageable dielectric
US5879572A (en) * 1996-11-19 1999-03-09 Delco Electronics Corporation Method of protecting silicon wafers during wet chemical etching
US6022670A (en) * 1997-05-08 2000-02-08 International Business Machines Corporation Process for high resolution photoimageable dielectric
US6680440B1 (en) 1998-02-23 2004-01-20 International Business Machines Corporation Circuitized structures produced by the methods of electroless plating
US6066889A (en) 1998-09-22 2000-05-23 International Business Machines Corporation Methods of selectively filling apertures
US6204456B1 (en) 1998-09-24 2001-03-20 International Business Machines Corporation Filling open through holes in a multilayer board
US6940160B1 (en) * 1999-03-16 2005-09-06 Seiko Epson Corporation Semiconductor device and method of manufacture thereof, circuit board, and electronic instrument
US6177357B1 (en) * 1999-04-30 2001-01-23 3M Innovative Properties Company Method for making flexible circuits
DE19955969A1 (de) * 1999-11-19 2001-05-31 Inst Mikrotechnik Mainz Gmbh Verwendung von Polyimid für Haftschichten und lithographisches Verfahren zur Herstellung von Mikrobauteilen
US6207350B1 (en) * 2000-01-18 2001-03-27 Headway Technologies, Inc. Corrosion inhibitor for NiCu for high performance writers
US9165821B2 (en) * 2013-12-23 2015-10-20 Infineon Technologies Ag Method for providing a self-aligned pad protection in a semiconductor device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3833436A (en) * 1972-09-05 1974-09-03 Buckbee Mears Co Etching of polyimide films
US4426253A (en) * 1981-12-03 1984-01-17 E. I. Du Pont De Nemours & Co. High speed etching of polyimide film
JPS58108229A (ja) * 1981-12-21 1983-06-28 Hitachi Ltd ポリイミド系樹脂膜の選択エツチング方法
US4523976A (en) * 1984-07-02 1985-06-18 Motorola, Inc. Method for forming semiconductor devices
US4606998A (en) * 1985-04-30 1986-08-19 International Business Machines Corporation Barrierless high-temperature lift-off process
JPS63122224A (ja) * 1986-11-12 1988-05-26 Nec Corp 薄膜混成集積回路

Also Published As

Publication number Publication date
EP0394638A3 (de) 1992-07-15
DE69031143T2 (de) 1998-02-12
US4911786A (en) 1990-03-27
EP0394638B1 (de) 1997-07-30
JPH0587978B2 (de) 1993-12-20
JPH02302053A (ja) 1990-12-14
EP0394638A2 (de) 1990-10-31

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Legal Events

Date Code Title Description
8330 Complete renunciation
8330 Complete renunciation