DE69024977D1 - Verfahren zur eliminierung von ätzsperrehinterschneidungen - Google Patents

Verfahren zur eliminierung von ätzsperrehinterschneidungen

Info

Publication number
DE69024977D1
DE69024977D1 DE69024977T DE69024977T DE69024977D1 DE 69024977 D1 DE69024977 D1 DE 69024977D1 DE 69024977 T DE69024977 T DE 69024977T DE 69024977 T DE69024977 T DE 69024977T DE 69024977 D1 DE69024977 D1 DE 69024977D1
Authority
DE
Germany
Prior art keywords
undercuts
lock
etch
eliminating
eliminating etch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69024977T
Other languages
English (en)
Other versions
DE69024977T2 (de
Inventor
John Cronin
Mark Lakritz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69024977D1 publication Critical patent/DE69024977D1/de
Application granted granted Critical
Publication of DE69024977T2 publication Critical patent/DE69024977T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
DE69024977T 1990-08-10 1990-11-07 Verfahren zur eliminierung von ätzsperrehinterschneidungen Expired - Fee Related DE69024977T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/565,574 US5118382A (en) 1990-08-10 1990-08-10 Elimination of etch stop undercut
PCT/US1990/006450 WO1992002951A1 (en) 1990-08-10 1990-11-07 Elimination of etch stop undercut

Publications (2)

Publication Number Publication Date
DE69024977D1 true DE69024977D1 (de) 1996-02-29
DE69024977T2 DE69024977T2 (de) 1996-08-08

Family

ID=24259232

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69024977T Expired - Fee Related DE69024977T2 (de) 1990-08-10 1990-11-07 Verfahren zur eliminierung von ätzsperrehinterschneidungen

Country Status (5)

Country Link
US (1) US5118382A (de)
EP (1) EP0542746B1 (de)
JP (1) JPH05507813A (de)
DE (1) DE69024977T2 (de)
WO (1) WO1992002951A1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5298463A (en) * 1991-08-30 1994-03-29 Micron Technology, Inc. Method of processing a semiconductor wafer using a contact etch stop
US5342808A (en) * 1992-03-12 1994-08-30 Hewlett-Packard Company Aperture size control for etched vias and metal contacts
US5254217A (en) * 1992-07-27 1993-10-19 Motorola, Inc. Method for fabricating a semiconductor device having a conductive metal oxide
US5292677A (en) * 1992-09-18 1994-03-08 Micron Technology, Inc. Reduced mask CMOS process for fabricating stacked capacitor multi-megabit dynamic random access memories utilizing single etch stop layer for contacts
JP4417439B2 (ja) * 1994-06-29 2010-02-17 フリースケール セミコンダクター インコーポレイテッド エッチング・ストップ層を利用する半導体装置構造とその方法
US5445976A (en) * 1994-08-09 1995-08-29 Texas Instruments Incorporated Method for producing bipolar transistor having reduced base-collector capacitance
KR0146246B1 (ko) * 1994-09-26 1998-11-02 김주용 반도체 소자 콘택 제조방법
US5759911A (en) * 1995-08-22 1998-06-02 International Business Machines Corporation Self-aligned metallurgy
US5960318A (en) * 1995-10-27 1999-09-28 Siemens Aktiengesellschaft Borderless contact etch process with sidewall spacer and selective isotropic etch process
JP2762976B2 (ja) * 1995-12-25 1998-06-11 日本電気株式会社 半導体装置の製造方法
DE19622415A1 (de) * 1996-06-04 1997-12-11 Siemens Ag CMOS-Halbleiterstruktur und Verfahren zur Herstellung derselben
US5923991A (en) * 1996-11-05 1999-07-13 International Business Machines Corporation Methods to prevent divot formation in shallow trench isolation areas
US6022782A (en) * 1997-05-30 2000-02-08 Stmicroelectronics, Inc. Method for forming integrated circuit transistors using sacrificial spacer
TW382783B (en) * 1998-07-06 2000-02-21 United Microelectronics Corp Method of making borderless contact
US7648871B2 (en) * 2005-10-21 2010-01-19 International Business Machines Corporation Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabricating same
US8790523B2 (en) * 2009-01-07 2014-07-29 Tdk Corporation Method for manufacturing magnetic head
CN101944484B (zh) * 2009-07-09 2012-10-03 上海华虹Nec电子有限公司 一种改善发射极窗口侧向开口的方法
DE102009052234A1 (de) 2009-11-06 2011-05-12 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Auf Waferebene herstellbarer Chip für Flüssigchromatographie sowie Verfahren für seine Herstellung
US8298930B2 (en) 2010-12-03 2012-10-30 International Business Machines Corporation Undercut-repair of barrier layer metallurgy for solder bumps and methods thereof
US9553044B2 (en) 2014-11-05 2017-01-24 International Business Machines Corporation Electrically conductive interconnect including via having increased contact surface area
CN108122834A (zh) * 2017-12-13 2018-06-05 上海华虹宏力半导体制造有限公司 一种改善接触孔中钨缺失的方法
CN112955401A (zh) * 2018-08-29 2021-06-11 宽腾矽公司 用于集成传感器器件的样本井制造技术及结构
CN110491833B (zh) * 2019-08-30 2021-12-03 上海华力微电子有限公司 金属互连线填充方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3764865A (en) * 1970-03-17 1973-10-09 Rca Corp Semiconductor devices having closely spaced contacts
IT1094517B (it) * 1978-04-28 1985-08-02 Componenti Elettronici Sgs Ate Procedimento per la fabbricazione di un elemento resistivo filiforme per circuito integrato
US4289574A (en) * 1979-04-30 1981-09-15 Fairchild Camera & Instrument Corp. Process for patterning metal connections on a semiconductor structure by using an aluminum oxide etch resistant layer
US4354896A (en) * 1980-08-05 1982-10-19 Texas Instruments Incorporated Formation of submicron substrate element
US4457820A (en) * 1981-12-24 1984-07-03 International Business Machines Corporation Two step plasma etching
GB8407907D0 (en) * 1984-03-27 1984-05-02 Sandoz Ltd Organic compounds
US4580330A (en) * 1984-06-15 1986-04-08 Texas Instruments Incorporated Integrated circuit isolation
US4759822A (en) * 1984-10-12 1988-07-26 Triquint Semiconductor Inc. Methods for producing an aperture in a surface
US4686000A (en) * 1985-04-02 1987-08-11 Heath Barbara A Self-aligned contact process
US4631113A (en) * 1985-12-23 1986-12-23 Signetics Corporation Method for manufacturing a narrow line of photosensitive material
US4838991A (en) * 1987-10-30 1989-06-13 International Business Machines Corporation Process for defining organic sidewall structures
US4892837A (en) * 1987-12-04 1990-01-09 Hitachi, Ltd. Method for manufacturing semiconductor integrated circuit device

Also Published As

Publication number Publication date
EP0542746A1 (de) 1993-05-26
DE69024977T2 (de) 1996-08-08
WO1992002951A1 (en) 1992-02-20
EP0542746B1 (de) 1996-01-17
US5118382A (en) 1992-06-02
JPH05507813A (ja) 1993-11-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee