DE69021899D1 - DMA-Steuerung. - Google Patents

DMA-Steuerung.

Info

Publication number
DE69021899D1
DE69021899D1 DE69021899T DE69021899T DE69021899D1 DE 69021899 D1 DE69021899 D1 DE 69021899D1 DE 69021899 T DE69021899 T DE 69021899T DE 69021899 T DE69021899 T DE 69021899T DE 69021899 D1 DE69021899 D1 DE 69021899D1
Authority
DE
Germany
Prior art keywords
dma control
dma
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69021899T
Other languages
English (en)
Other versions
DE69021899T2 (de
Inventor
Richard G Fogg
Joseph Richard Mathis
James Otto Nicholson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69021899D1 publication Critical patent/DE69021899D1/de
Application granted granted Critical
Publication of DE69021899T2 publication Critical patent/DE69021899T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
DE69021899T 1989-01-13 1990-01-11 DMA-Steuerung. Expired - Fee Related DE69021899T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/297,778 US5251303A (en) 1989-01-13 1989-01-13 System for DMA block data transfer based on linked control blocks

Publications (2)

Publication Number Publication Date
DE69021899D1 true DE69021899D1 (de) 1995-10-05
DE69021899T2 DE69021899T2 (de) 1996-04-18

Family

ID=23147703

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69021899T Expired - Fee Related DE69021899T2 (de) 1989-01-13 1990-01-11 DMA-Steuerung.

Country Status (4)

Country Link
US (1) US5251303A (de)
EP (1) EP0378423B1 (de)
JP (1) JPH0623968B2 (de)
DE (1) DE69021899T2 (de)

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Also Published As

Publication number Publication date
EP0378423B1 (de) 1995-08-30
JPH02227763A (ja) 1990-09-10
DE69021899T2 (de) 1996-04-18
US5251303A (en) 1993-10-05
EP0378423A2 (de) 1990-07-18
JPH0623968B2 (ja) 1994-03-30
EP0378423A3 (de) 1991-05-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee