TW583547B - Linked-list memory-access control for a concentrator - Google Patents

Abstract

A microprocessor system employs a linked-list structure for a direct memory-access controller to service requests by one or more data pumps. Such direct memory-access controller may be termed a linked-list, direct memory-access controller (LLDMAC). The central microprocessor periodically polls, e.g., a status register in each data pump to determine which data pumps to service. Using information from each status register, the central microprocessor programs the LLDMAC and corresponding locations of system memory buffers in the microprocessor system allocated to each data pump for service. The central microprocessor programs the LLDMAC and corresponding locations of system memory buffers such that a chain linking addresses of each data pump to service, termed a linked chain, is formed by the pointer information stored in the system memory buffers. Once the linked chain to address data pumps for service is formed, the central microprocessor causes the LLDMAC to begin the data transfer for the first data pump service of the linked chain, and then returns to other processing tasks. The LLDMAC transfers the data between system memory and the data pumps for each service in the chain, and then indicates to the central microprocessor when the services of the linked chain are complete.

Description

V. Invention Description G)

This ^ Ming system is a "scoop transfer" in the signal processing phase. __ Controlling the processor and the memory: In many signal processing applications, the capabilities of the same tribute generator and processor are configured; ::: Management control and management of data in the concentrator, pumping data such as the "dagger". ; And the system memory between the information age household 1 for the special data transfer wheel ^ for the application-specific circuit or processing 仏 number to coordinate the use ;; use each data pump implementation, 'for example V. 90, v. 34, wait. The transfer of data between human communication networks or the temporary storage of more than one data pump can be read by the central microprocessor. If the information indicates a data pump; poll the status of each data pump. Move the system memory and services required for the month. The central microprocessor transfers a large amount of data on the transfer bus: the data in Yuryu. If the processing power of the central processor. At present, each data transfer generally requires a medium. The central microprocessor is involved, and the medium = raw data transfer processing, that is, the straightforward ability (that is, the microprocessor bandwidth) is used for the t processor because most of its As a whole, the microprocessor is used as the material transfer operation, so it will adversely affect the rate of the previous technology. The transfer of the management data of the memory access controller in the direct memory access (DMA) controller is controlled by Jieji i4 ° midnight, and therefore, the «end processor directly manages various data pumps is lifted. Associated with the system, the memory of the bamboo's slavery system performance. The central microprocessor needs to serve from each -------

Page 6 of 583547 V. Description of the invention (2) One ___ Table: Ϊ Chestnut ΐ 彳: 彳: ^: and put the received request into this table in order of priority to transfer the data: the second and second control are directly After the data in Lipu, the middle, ::, and two-shellfish pumps. When the service is completed, the controller transfers data to / from the computer, and the program is controlled by direct memory access. After each service is completed, all data in Lipu? Seeking the second program-controlled direct memory access controller. < 、 Micro-Processing State Phase Invented about direct memory access * ^ ^ ^ ^ ^ ^ ^ structure ′ one or more linked list address addresses of its processing service need to be served! The data pump generates the address sequence. It contains the data system's buffer, which buffers the crying packets. The pump address and the next ramp in the sequence are used as packet buffer indicators. Axekou_ # 六 // / System memory memory buffer crying ::: f memory controller and system log form secret location, but the service information stored in the system memory buffer cry The position of the pump:: the data pump of the second t service, the central processing module makes the connection directly; linking. The controller opens the private m ^ 'and directly accesses the memory. Central processing 2: linking The first data pumping service transfers data to the heart-moving system; t returns to other processing tasks. The direct-access memory controls the cries to be dried on the data of the fruit tree in the link body and the bond key, and when the service for the labor center to process the cries or more material pumps is completed, the cries can indicate ί °° Data transfer completed. Jiajia's scope of patent application and related drawings will be detailed below, attached-> 1 583547 V. Description of the invention (3) Features and advantages Related drawings include a fuller understanding of other aspects of the present invention including ... m shows that the data pool concentrator according to an exemplary embodiment of the present invention includes a central microprocessor and a straight edge 'edge number link list (LLMAC); [Figure 2 of the limb access controller shows the system memory buffer package used in the embodiment of the present invention; the structure of the number, this figure 3 shows the embodiment of the system memory buffer cry The target example of the chain name W, which is used by the present invention, the _ key, lists the direct memory access controller to implement the data transfer from the port data to the inbound data. Figure 4 shows the implementation of the present invention. An example shifting flowchart; and FIG. 5 is a shifting flowchart of an example of the present invention. Foreign description A processor system borrowing an alpha structure according to the present invention, the link list of the memory access controller is a pump request. In the present invention, the memory access controller is generally used to serve one or more data. In the embodiment described herein, the direct memory (lldmac) is used. The processor 糸: f-line direct memory access controller fetches the controller, which reduces the ^ ,, and 'errors caused by the use of the linked list of direct memory storage, and increases the processing and celigial capacity for processing data transfer operations Yes, the CPU week: the performance of the system. According to the preferred embodiment of the present invention, the composite state register is polled in place, for example, among all data pumps, the data pump that determines which service is to be served. Chinese. French Handling. 583547

The body access controller using each composite state register and the body buffer position of the corresponding system are centrally processed. Because the central processor program-controlled link corresponds to the system memory buffer bit pumped address, a chain (called a "chain" stores this link together with the information in the system memory buffer. Once the program, the central The processor causes the linked list to perform the task for the first data served by the key. The linked list is composed of all the linked lists and all the linked lists in the direct memory access controller. Indicate when the CPU is finished. Although the implementation examples of the present invention will be described next, the embodiments of the present invention can be applied to any management data converter to directly manage the efficiency or effectiveness of many data pumps and systems. Those who are based on microprocessors should understand that other processors, computers, programmable logic or other non-applied devices can be used here. These processors can be listed in the flood and program-controlled links. Directly remember the location of the memory buffer, the system register is configured to the data that needs service, and the list is directly linked to the memory access control, so the data link of all services is linked. link ed chain)), and the direct memory access controller that controls the link chain and system memory buffer line allocated to the corresponding data pump starts pumping data, and then returns to its direct memory access The controller transfers data between system data. The link uses interrupts or status bits in the register to form the service of the chain. The microprocessor-based data set is not limited to this. When the system is implemented, the data transfer between the memory of the central processing system is canceled. In addition, the implementation example described below is a physical computer system. However, the microprocessor is well-known for the purpose of demonstration. Whether the signal processing tube is implemented in the specific use of the integrated circuit for the specific implementation of the embodiment of the present invention,

Page 9 583547 V. Description of Invention (5)-OK. FIG. 1 shows a data pool concentrator 100 using a microprocessor system 101, and the microprocessor system 101 includes a linked list direct memory access controller 1 02 and a central microprocessor 1 03 . Microprocessor system 1 0 1 Uses linked list direct memory access controller 1 0 2 Manages data pumps 111 (1)-111 (n), central microprocessor 103 and data between system memory Transfer, the system memory includes a system random access memory 11 2 and a read-only memory 1 1 3. The microprocessor system 101, the data pump 丨 丨 丨 ^^ 丨 丨 ") and the system memory including the system random access memory 11 2 and the read-only memory 11 3 are coupled to the system memory bus 1 1 0 And transfer data on the system memory bus 110. The system memory bus 110 includes the address bus that reads and writes memory addresses and the data bus that reads and writes data values. The address and data buses It can be practically implemented on the bus structure using time multiplexing technology. Data transfer may be 'for example, by data pumping 丨 n (1) _ 丨 丨 丨 (N) coordinating and / or processing individual modem pairs Talk about related information. Arbiter of microprocessor system 〇1 丨 〇4 can be used to provide shared memory between the central microprocessor 103 and the linked list direct memory access controller 102 Row 11 0. High-speed interface 1 0 5 Management data transfer between the central microprocessor 10 3 of the communication and microprocessor system 101 and an external source, which may be, for example, a central exchange (not shown in FIG. 1) ). Coordinated by data pump 111 (1) -1 lj (N) and / Handle the conversation between individual modems, which can be used to transfer data between the user and the center. The data exchanged between the user and the center is transferred to the data pool in a signal form via a communication line such as T1 or E1. . Device. T1 line carrying. 2 4 use

Page 10 583547--^^ V. Description of the invention (6) The user channel, the bandwidth of each user channel is 64 kbits / s, and the time is multiplied by 1. 5 4 4 Mb its / s chain link Inbound and outbound traffic. The E 1 line carries 30 user channels, and the bandwidth of each user channel is 64 k b i t s / s. The time multiplexing is used to chain each flow direction in 2. 0 4 8 M b i t s / s. Time slot switch 121 is a gangster that transfers valid data channels between one or more T1 and / or £ 1 lines and the data pump using the corresponding slot 1 1 1 (1)-1 1 1 (N) For example, if the above is true, the 128-slot time-multiplexed bus (TDM) 120 operates at 8.192 MbUs / s. Whenever a data conversation begins, the time slot of the time-multiplexed bus is dynamically assigned to each data pump m (1)-1 1 1 (N). When a data conversation is removed, the slot is vacated, and then when another data conversation begins, the slot can be assigned to another data pump. '' The effective data pump corresponding to the data processed by the central microprocessor 103 is pumped / and the processed data is transmitted to and from the center exchange via the high-speed interface. μ The implementation examples described below are related to circuit switching networks, pumps and telecommunications lines, or old interfaces, and processing data. However, those who are skilled in the technology should understand that pumping U1 (1) -111 (N) can be expected and other forms of data, such as voice, audio tape or special digital owe, received from, for example, data packets (news The box or unit relays the electricity to cry # + 贝 线 to implement :: bu, also can use other types of communication to support other types of Xu,, 隹 r, Yitong k,, spring, and branch i; t shows the quasi interface ( (For example, SQNET). Also about the data pool concentrator 丨 〇〇 Fan basin material bus these 7 people, τ the central processor 1 0 3 assets. 'T implementation of 8-bit, 16-bit .Bit and / or 32-bit_turn 1

583547 V. Description of Invention (7) Homework. Data pumps 111 (1)-111 (N) can be 16-bit peripherals, and data pumps 111 (1)-111 (N) can use index memory buffers to store inbound data ( Such as user-to-center exchanges) and out-of-port data (such as from center-to-user exchanges) to transfer processing data. This is a brief description of the operation of the index memory buffer. The central microprocessor 1 0 3 can allocate addresses to the system read-only memory 11 3, the system random access memory 11 2 and the data pump 1 1 1 (1)-111 (n). Two addresses are assigned to all data pumps 111 (1) — 1 丨 丨 (N): the first data pump address is used to address a specific data pump, and the second data pump address is used To address the corresponding data pump data to and from system memory. The central microprocessor 103 generates a read / write (R / W) signal, which controls the transfer of data from the data pump to the central exchange (read signal), or from the central exchange to the data pump (write Incoming signal). In addition, the central microprocessor 103 polls the data pumps served 丨 丨 1 (丨) — 丨 丨 丨 (N), or receives one or more data pump requests, and assigns corresponding data pumps. The system memory buffer pumps data for one or more services 丨 丨 丨 (丨) — 丨 丨 丨 (N). Regarding the example of the above addressing scheme, the data pump 丨 丨 丨 (丨) can use the memory space in the system memory starting with DPADD (1), and the first data pump address DPADD (l) and the first The second data pump address DPADD ((l) + 2) corresponds to the start address DPADD (1) of the memory space. Memory space involves all available and addressable fishing memory, including system random access memory 11 2. · system read-only memory! } 3. Memory buffers in the data pumps i (j) -iij (N) and the internal memory (not shown) of the microprocessor system 1 〇 enough to list the direct memory access controller 丨〇2 Random for slave, system

Page 12 583547 5. Description of the invention (9) Used to drive the data bus. Bonding the table direct memory access controller 丨 〇2 uses the individual system's redundant memory data buffer located in the system random access memory 11 2 or the microprocessor system 丨 01 to transfer the central microcomputer Data between the processor 丨 〇3 and the effective data pump in the data pump Π1 (1)-111 (N). The central microprocessor 103 and the linked list direct memory access controller 丨 〇2 uses read and write indicators to address, and transfer data to and from the system memory buffer. For outbound data, it maintains two indicators One is to instruct the central microprocessor 103 to fill each system memory buffer, and the other is to instruct the linked list direct memory access controller 02 to retrieve data. For out-of-port data, the central microprocessor 103 processes the corresponding data-pumped data and stores it in a separate system memory buffer. And all the system memory buffers are used in a circular manner. · The central microprocessor 1103 stores the data in consecutive locations, and the linked list direct memory access controller i Q2 fetches the data from this location and transfers it. The data goes to the respective memory buffers of the data Guopu as described previously. The same applies to inbound data. The central microprocessor 103 then uses and updates the write indicator of the outbound data. The linked list and direct memory access controller 102 uses a corresponding index, and the corresponding index is the reading index of LLDM> AC 102 from the data. When the central processing unit 103 sets one of the memory buffers to the corresponding data (Lipu 111 (1) -11UN), the central processing unit 103 initializes the linked list directly. The memory access controller 10 is used as a reading indicator for the out-of-port spring material. According to the normal operation, for outbound data, link list direct memory access

Page 14 583547 V. Description of the invention (ίο) The reading index of the controller 102 is dragged to the writing index of the central microprocessor 103. The two indicators are cyclic (ie, when the end position of the system memory buffer is reached, each index wraps around to the start position).

Regarding the separation data, the central microprocessor 1 0 3 processes the corresponding data Kuriura 11 1 (1)-1 1 1 (N) data, and also uses the system memory buffer in a circular manner. The linked list direct memory access controller 102 stores data in consecutive locations in the system memory buffer, and the central microprocessor 103 retrieves data from that location for processing. The write indicator is used and updated by the direct memory access controller 10 2 of the key list, but the read indicator is used and updated by the central microprocessor 103. When the central microprocessor 103 sets the system to record billions of data: the buffer pumps one of the corresponding data pumps 11 1 (1)-111 (N), the central microprocessor 1 0 3 initializes the linked list directly Memory access controller 丨 0 2 Read indicator for inbound data. According to the regular operation, the reading index of the central microprocessor 1 0 3 drags the writing index of the direct memory access controller 丨 0 2, which is similar to the data transfer of outbound data flow. As in the case of out-of-port data, when the end position of the system memory buffer is reached, two pointers surround. To the start position.

The linked list direct memory access controller 1 0 2 uses information about all data pumps 111 (1)-111 (N). The information includes the following parameters and is shown in Figure 2: Current LLDMAC Pointer, Pointer to the Next Buffer i the Chain ’Data Pump Address, Data Pump Memory Buffer Pointer 5 Buffer Size j Transfer Count, and End Signature. The central micro processor 103 configures a memory buffer for each data stream pumped by a different data.

Page 15 583547 5. Description of the invention (11) Some parameters are stored at the beginning of each memory buffer. FIG. 2 is an example of a memory structure including a system memory buffer 200 including parameters. The size of the system memory buffer 200 is up to 6 5 5 3 6 16-bit words. The data words representing information can be 8-bit words, 16-bit words, or 32-bit words. Unless otherwise specified, it is assumed to be 3 2 -bit words. The first data word 2 0 1 indicates the index of the current system memory buffer (the parameter is defined as " Current LLDMAC Pointer1 ') used by the linked list direct memory access controller. The second data word 202 indicates the next link in the chain

The system § has an index of the memory buffer, and points to the beginning of the system memory buffer (the parameter is defined as 1P0inter t0 the Next Buffer in the Chain ". The third data word 2 03 is used to store the first Data pump address. This address is used for the system memory buffer corresponding to the data pump (the parameter is defined as "Data Pump Address"). If a previously defined offset is used, the second data pump address can be driven by the first data pump address. For the example described here, since the word length of the data pump address is 6_bits, the offset between the first and second data pump addresses is two. The fourth tribute word 204 refers to the index of the memory buffer in the data pump (the parameter meaning is " Data Pump Memory Buffer Pointer1, ". First

The five-word tribute represents the following three fields: The first field 2 0 5 is a 6-bit bit 'used to indicate the size of the memory buffer (the parameter is defined as " fer Size1). The second field 206 is a multi-bit data word, which is used to represent the data transfer a ten digits (the parameter is defined as " Transfer c〇untπ). The third field 207 is an 8-bit data word as the end identification flag regardless of whether the system memory buffer is the last one in the chain (the parameter is defined as " End

Page 16 583547 V. Description of the invention (12) For example, if the hexadecimal value 00h is used to indicate that the system memory buffer 1 is in the middle of Kaizhi and the link chain, and the value FFH can be expressed as: Six: Data word 208 indicates Central microprocessor 103 value ': After the central microprocessor 103 processes the data from the system memory buffer, the processor H3 updates the current index value. And the stored data from the 7th two two masters 2G9. Regarding the described embodiment, its data = storage area is approximately (Buffer Size_12) 16_ byte characters. (Each 32: bit ^ tribute word is equal to two 16_bit data words). The central microprocessor 1 03 initializes the first six words of the system memory buffer before the initial data transfer of the physical access controller 1 02 in the linked list. . . FIG. 3 shows an example of a chain using four system memory buffers—states 2 0 0 (1) to 2 0 0 (4) in an embodiment of the present invention. System memory buffer 2 0 (1) corresponds to the data pump 1 of the service, and then the parameter Pointer to Next Buffer value of the system memory buffer 200 (1) is used to set the system memory buffer for the next service 2 0 0 (2). The system memory buffer 2 0 0 (2) corresponds to the service data pump 4 and then uses the parameter Pin ter to Next Buffer value of the system 1 memory buffer 200 (2) to set the next service. System memory buffer 2 0 0 (3). The system memory buffer 2 0 0 (3) corresponds to the data pump 2 of the service, and then the parameter Pointer to Next Buffer value of the system memory buffer 2 0 0 (3) is used to set the next, and it is the last service Jun system memory buffer 2000 (4). The system memory buffer 2 0 (4) corresponds to the service data pump 3. The end of the fifth word of the last system memory buffer 2 0 0. (4) in the chain is FFH, which indicates the system and system memory_

Page 17 583547 V. Description of the invention (13) Buffer 2 0 0 (4) is the last system memory buffer in the chain. In addition, for the system memory buffer 20 0 (4), it means that the second word pointing to the next two system memory buffers in the link is invalid. The value of the end identification flag field corresponding to the system memory buffer 2 0 0 (1)-2 0 0 (3) is 0 0H. The system memory buffer 2000) is set by the microprocessor with a corresponding linked list, which is a dedicated register of the physical access controller 1 Q 2. When transferring outbound data, the dedicated register is the outbound buffer index register (OBPR) 'to store the current system memory buffer index, and when transferring inbound data, the inbound buffer index The temporary register (IBPR) is used to store the current system memory buffer index. The microprocessor system 101 includes seven temporary registers that can be used to temporarily hold the parameters of the corresponding system memory buffers. The seven temporary storage parameters are: Current LLDMAC Pointer ’Pointer to the Next Buffer in the Chain, Data Pump Address, Data Pump Memory Buffer Pointer, Buffer Size,

Transfer Count and End Signature. The initial value of the future End Signature in the temporary register is set to 00H, and the parameter Transfer Count held by the temporary register is reduced by 1 (for example, it can be implemented like a down counter). Implementation example, flowchart of data transfer for outbound data processing. For example, the central processing unit 103 (Fig. 1) initializes the data transfer to one or more of the data pumps 111 (1) -111 (N) requesting service at step 401. At step 401, the central processing unit 103 sets the out-of-port buffer index, and the value of the register is used as the first system memory in the corresponding chain and link.

Page 18 583547 V. Description of the invention (14) The index value of the buffer and sends a start command to the linked list direct memory access controller 102. At step 402, the parameters of the system memory buffer of the corresponding service data Lipu (its address is marked by OBPR) will be loaded from the linked list direct memory access controller 丨 〇2 Corresponding temporary / time register. At the beginning of step 403, the temporary register stores the corresponding parameters.

Data Pump Memory Buffer Address and Data Pump

The content of Address (that is, the first data pump address) is written from the linked list directly to the memory access controller 102 to the system memory bus 丨 丨 〇. As described in the previous month, the process involves placing the first data pump address on the address bus (ie, the value of the parameter "" pump Address stored in the temporary register) so that it corresponds to Data pumps m (1) — 111 (N) were able to confirm that they were being serviced. The process then moves the memory buffer indicators in the data pump (that is, the parameters stored in the temporary

Memory Buff er Pointer) to the data bus. > In step 404, a value of 2 may be used to increase the value of the Data Pump Address (called the data pump address (DPA) to maintain temporary storage) in the temporary register, thereby setting the parameter. The value of the Data Pump Address is converted to the ^ = lilipu address, and the 6-bit Wubei material value of the current system memory buffer is loaded into the temporary register used by the lean material. The 16-bit data value is addressed by the parameter Current lldMAC Pointer. At step 40, the value of the parameter Current LLDMAC Pointer is compared with the end address of the system memory buffer. If the comparison values in step 40 5 are equal, then in step 4 06, it will be temporarily stored

Page 19 583547 Five 'invention description (15) The value of the parameter Current LLDMAC Pointer in the device is reset to the index value of the first address or the beginning of the data area (for example, the field of system memory buffer is equivalent to 0BPR + 1 2 ). If the two comparison values in step 4 0 5 are not equal, then in step 40 7, the value of the parameter Current LLDMAC Pointer in the temporary register is increased by 2 and the value is used to point to the position of the next data area. The process proceeds from step 406 or step 407 to step 408. In step 408, the content of the data register is written into the position of the parameter Data pump Address + 2, and the value is indicated by the value in the DPA holding register. At step 409, the decrement of the Trans; fer c〇unt value held by the temporary register is 1. At step 4 10, the test judges whether the value of the parameter Transfer Count in the temporary register is zero. If the test in step 4 1 q temporarily holds that the value of the parameter Transf er Count in the register is not zero, the process returns to step 404 to load the data value of the next current system memory buffer. However, if the test in Step 4 〇 temporarily determines that the parameter Transfer Count in the register is temporarily held at zero, then in step η 1, it will test to determine whether the value of the parameter End Signature is FFH. If the parameter En (1 Signature value of FFH is determined by the system memory buffer test in step 411, the value of Curren1: llDMAC Pointer will be updated at step 412. The updated value of the current LLDMAC Pointer will involve Load the value from the temporary register into the first word of the system memory buffer. The process is aborted at step 4 1 5 'However, step 4 6 is optional, either before step 4 5 or at step 5 After 4 1 5, it is used to interrupt the central microprocessor 丨 〇3 and indicate that the process is completed. If the test parameter is determined in step 411, the value of 1 (1 signature is not gFFIj

Page 20 583547 V. Description of the invention (16) ----- At step 41 3, write the value of the parameter LLDMAC P 0 i n t e r of the holding register into the first word of the system memory buffer. Then, at step 414, the values of the parameters p0inter "and t〇⑽ N ^ xt puffer ln the chain are loaded from the corresponding temporary registers into the off-port buffer index register. The results are stored in the off-port The address value of the buffer index register will point to the next system memory buffer in the link (ie, the next service = material pump), and the process returns to step 4 and repeats the process until Until the last data buffer is reached, the parameter End Signature is marked as FFH value. Figure 5 is a flow chart of transferring inbound port data processing data according to an example of the embodiment of the present invention. For example, a central microprocessor 丨 〇 3 (Figure 丨) At step 501, the initialization data is transferred to one or more of the data pumps requesting service 丨 丨 丨 (丨) — 丨 丨 丨 (N). At step 501, the central microcomputer The processor 丨 〇3 takes the index value program-controlled inbound buffer corresponding to the first system memory buffer address in the link as an index register, and issues a start instruction to LLDMAC 1 02. At step 5 0 2 At that time, there will be related service data pumps (which The parameters of the system memory buffer (addressed by I BPR.) Are loaded into the corresponding temporary registers by the linked list direct memory access controller 1 02. When step 503 starts, temporarily Register to store corresponding parameters

Data Pump Memory Buffer Address and Data Pump

The content of Address (that is, the first data Cypress address) is directly written into the system bus 11 by the memory access controller link list 102. As described previously, the process involves placing the first data pump address on the address bus (ie, the value of the parameter Data Pump Address), and loading the corresponding data,

Page 21 583547 V. Description of Invention (17) Pu 1 11 (1)-111 (N) was able to confirm that he was being served. The process then writes the memory buffer index (ie, the value of the Data Pump Memory Buffer Point) in the data pump to the data pool. L j is not on. At step 5 04, the value 2 can be used to increase the temporary temporary The value of the parameter Data Pump Address stored in the register (called the data pump address (liver) holding register) 'It converts the value of the parameter Data Pump Address to the second data pump address, and The 16-bit data value of the current system memory buffer is loaded into a temporary register ("da ta register") used by the data, and the 16-bit data value is determined by the parameter Data Pump Address Addressed by value added. In step 505, the 16-bit data value in the data register: is written to the current system memory buffer location, and the location is addressed by the current LLDMAC Pointer. At step 506 ', the value of the parameter Current LLDMAC Pointer is compared with the end address of the data buffer. If the two comparison values in step 5 and 0 are equal, then in step 50 and 7, the value of the parameter ⑸ ^ ⑽ 士 LLDMAC Pointer in the temporary register is reset to the index value or data of the first address. The beginning of the region (for example, the field where 纟 is the memory buffer is equivalent to IB pr + 1 2). If the two comparison values in step 5 06 are not equal, then in step 5 08, the parameter in the temporary register Curren1: LLMAC Pointer value is increased by 2 and this value is used to point to the current system The location of a lean area below the memory buffer. The process proceeds from step 507 or step 508 to step 509. At step 5 0 9 the temporary register holds it. The decrement of "^ ⑽ 以 值" minus 1 is 1. At step 5 1 0, test and judge to temporarily hold one of the temporary registers-

583547 V. Description of the invention (18)

Whether the Transfer Count value is zero. If it is judged in step 51o that the Transfer Count value in the temporary holding register is not zero, the process returns to step 5 0 4 'to read the next data value and put it into the data register. However, if the test in step 510 judges that the ransfer c0unt value in the register is temporarily held ^ zero ', then in step 511', it is tested to determine whether the value of the parameter End Slgnature is FFH. If the test in step 51 1 determines that the parameter End Signature of the system memory buffer is FFH, then in step 512, the value of the current number LLDMAC Pointer will be updated. The update parameter Current LLDMAC Pointer involves loading the updated value from the temporary register into the first word of the system memory buffer. The process is aborted at step 5 丨 5, however the optional step 5 1 6 is either before step 5 1 5 or after step 5 5 5 'is used to interrupt the central microprocessor 丨 03 and instruct the process · It has been completed if the test judgment parameter En (i Signature value is not FFH 'in step 511', in step 513, the value of the holding register parameter Curren1: LLDMAC Pointer is written into the first word of the system memory buffer Then, at step 514, the value of the parameter p ^ inter to the Next Buffer in the Chain from the corresponding temporary register is loaded into the inbound buffer indicator register. The result is stored in the inbound buffer The address value of the device index register will point to the next system memory buffer (ie, the data pump for the next service) in the link, and the process returns to step 502 and repeats the above process until it reaches The final data buffer is like the FFH value to indicate the parameter End Signature.

The microprocessor system operation according to the embodiment of the present invention can be cancelled by

Page 23 583547 If you do this, you can also implement this process, you can also change the process of other machine code samples, stored in the storage media, or borrowed from general-purpose components, for example, you should understand the principle and changes. The form of the device and the device formally embody the magnetic disk and optical disc storage medium of the present invention, in which, the machine becomes a physical form, which is loaded and / or executed. For example, via a wire, when the machine is loaded into a practical version Invented the code segment set logic circuit. It is not necessary to violate the detailed description, materials and arrangements in order to explain the typical transmission of the material flow and increase grievances. In addition, the link allows the data served by the system to pump dynamic links, thereby expanding the system. Examples of circuit processing, but those skilled in the art should understand that electricity: the digital field's software programs; for example, digital signal processors, five, invention description (19) central processing of its industry The performance, the memory buffer, and the micro-control of various components that allow the circuit components to be used in spite of the invention have not been described, can be implemented in the same manner or any implementation. In the same way, regardless of the transmission of the fiber-optic code, there is a variety of processors in one unique advantage. For example, the data pool group only corresponds to the need for $ state link form. The invention is related to this. Well-known functions can also be implemented. This software can be used in the form of a code, such as a general purpose electric month, such as a readable storage of a debtor, such as a computer, or a code storage medium can be input by a machine. This transmission medium is emitted by electromagnetic radiation. The brain, on the processor of the machine, its operation is close to $ 1. If you are familiar with this technical field, you can elaborate and materialize the invention. Tangible media, hard-type devices, when the machine loads and implements the invention of the invention ', for example, or via a cable, a device that penetrates and executes the process. When the practical processor is provided in the following application, special arrangements and other parts are included in the essence of the invention

Page 24 583547 V. Description of Invention (20) has been described and explained above

Claims (1)

583547 VI. Scope of patent application '-1 · A matter for transferring data of one or more data pumps ^ The device includes ..., a central processing unit, and the functions of the central processing unit are: 丨) A chain link corresponding to the address sequence of one or more data pumps ^ 彡 配置 Equipment 3 buffers for each material pump, the memory buffer stores the corresponding two material pumps If the sequence contains more than one of the following: the address index of the memory buffer corresponds to the address of the lower_sense 4 pump in the sequence; and a memory access controller Is used to respond to the CPU's number to process the current data transfer between the corresponding memory buffer and the corresponding memory pump and memory g, | & where 1) the memory access controller is based on the current memory The index of the body buffer confirms the memory buffer of the next processing. If there is a next processing G 己 memory buffer, then 2) sequentially transfer the data of one or more data pumps corresponding to the link. . 2. The device according to item 1 in the scope of the patent application, wherein the memory buffer includes a data length value and the memory access controller fills the memory buffer with corresponding data pumped data according to the data length value . 3. The device according to item 1 in the scope of the patent application, wherein the memory buffer includes an end identification flag value, which indicates whether the current memory buffer is the last memory in the chain, and the memory stores Take the controller to terminate the processing of the memory buffer in the link according to the values of the end identification flag. 4 · As in the first item of the scope of the patent application < device, each data pump Page 27 583547 6. Scope of patent application Including an internal data pump memory buffer and an index index located in the buffer, the index index successively transfers data in or out according to the processing of the memory access controller. 5. The device according to item 1 in the scope of patent application, wherein when the memory access controller processes one or more data-pumped memory buffers in the chain, the central processing unit performs other processing tasks. 6 · The device according to item 1 in the scope of patent application, wherein the device is embodied by an integrated circuit. 7 · The device in the first item in the scope of patent application, wherein the device is embodied by a data pool, and each data pump processes the data. 8 · A method for transferring one or more data pumped data, the method includes the following steps: a) forming a link chain corresponding to one or more data pumped address sequences; b) for each Each data pump is configured with a memory buffer. The memory buffer includes 1) the address corresponding to the lean system pump ^ if the sequence contains more than one address, 2) the address index of the memory buffer corresponds to the sequence The address of the next data pump; and c) the current memory buffer in process transfers data between the corresponding data pump and the current memory buffer by: c 1) according to the current memory The index of the buffer confirms the memory buffer of the next processing. If there is a memory buffer of the next processing, c2) transfers the data corresponding to one or more data pumps in the sequence of the link chain. _ 9. The method according to item 8 in the scope of patent application, wherein the memory buffer Page 28 583547 6. The scope of patent application includes the data length value, and the method further includes the step of filling the memory buffer with the corresponding data pumped data according to the data length value. I 0 · The method according to item 8 in the scope of the patent application, wherein the memory buffer includes an end identification flag value indicating whether the current memory buffer is the last memory buffer in the link chain, and the The method further includes the step of discontinuing the processing of the memory buffer in the link based on the end identification flag value. II. The method of item 8 in the scope of the patent application, wherein each data pump includes an internal data pump memory buffer, and is located in the buffer when the corresponding memory buffer is processed in step c) The index index of has been turned over successively: input or output data. 1 2. The method according to item 8 in the scope of patent application, wherein the method is implemented on at least one processor that is embodied by an integrated circuit. 1 3 · The method of item 8 in the scope of patent application, wherein the method is implemented in the processor of the data pool concentrator, and the data transferred between the corresponding data pump and the current memory buffer transferred in step c) is data . 1 4. A computer-readable medium having a plurality of instructions stored thereon, the plurality of instructions including instructions executed by a processor, and when the processor executes these instructions, it will cause the processor to execute data Transfer method, which method is used for one or more data pumps, and the method consists of the following steps: a) forming a link chain corresponding to one or more data pumped address sequences; b) pair Each data pump is configured with a memory buffer. The memory buffer includes 1) the address corresponding to the data pump. If the sequence contains more than one address, Page 29 583547 VI. Addresses above the scope of patent application, 2) The address index of the memory buffer corresponds to the address of the next data pump in the sequence; and c) The current memory buffer in process uses the following c 1) and c 2) to transfer the data between the corresponding data pump and the current memory buffer: c 1) Confirm the next processing memory buffer according to the current memory buffer index. The processing memory buffer, then c 2) transfers the data corresponding to one or more data pumps in the linked sequence. Page 30