DE69020708D1 - Verfahren zur Herstellung von biMOS-Halbleiterbauelementen mit verbesserter Schnelligkeit und Zuverlässigkeit. - Google Patents

Verfahren zur Herstellung von biMOS-Halbleiterbauelementen mit verbesserter Schnelligkeit und Zuverlässigkeit.

Info

Publication number
DE69020708D1
DE69020708D1 DE69020708T DE69020708T DE69020708D1 DE 69020708 D1 DE69020708 D1 DE 69020708D1 DE 69020708 T DE69020708 T DE 69020708T DE 69020708 T DE69020708 T DE 69020708T DE 69020708 D1 DE69020708 D1 DE 69020708D1
Authority
DE
Germany
Prior art keywords
reliability
production
semiconductor components
improved speed
bimos semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69020708T
Other languages
English (en)
Other versions
DE69020708T2 (de
Inventor
Ko Tsubone
Yoshio Umemura
Kouichi Shimoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Application granted granted Critical
Publication of DE69020708D1 publication Critical patent/DE69020708D1/de
Publication of DE69020708T2 publication Critical patent/DE69020708T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/009—Bi-MOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
DE69020708T 1989-12-27 1990-12-27 Verfahren zur Herstellung von biMOS-Halbleiterbauelementen mit verbesserter Schnelligkeit und Zuverlässigkeit. Expired - Fee Related DE69020708T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1336387A JPH03198371A (ja) 1989-12-27 1989-12-27 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69020708D1 true DE69020708D1 (de) 1995-08-10
DE69020708T2 DE69020708T2 (de) 1996-03-14

Family

ID=18298609

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69020708T Expired - Fee Related DE69020708T2 (de) 1989-12-27 1990-12-27 Verfahren zur Herstellung von biMOS-Halbleiterbauelementen mit verbesserter Schnelligkeit und Zuverlässigkeit.

Country Status (5)

Country Link
US (1) US5100815A (de)
EP (1) EP0435257B1 (de)
JP (1) JPH03198371A (de)
KR (1) KR0152078B1 (de)
DE (1) DE69020708T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5234844A (en) * 1988-03-10 1993-08-10 Oki Electric Industry Co., Inc. Process for forming bipolar transistor structure
US5219768A (en) * 1989-05-10 1993-06-15 Oki Electric Industry Co., Ltd. Method for fabricating a semiconductor device
EP0768709B1 (de) * 1990-11-14 2005-02-16 Samsung Semiconductor, Inc. BiCMOS-Verfahren mit Bipolartransistor mit geringem Basis-Rekombinationsstrom
JP2625602B2 (ja) * 1991-01-18 1997-07-02 インターナショナル・ビジネス・マシーンズ・コーポレイション 集積回路デバイスの製造プロセス
FR2679380B1 (fr) * 1991-07-16 1997-11-21 Thomson Composants Militaires Procede de fabrication de circuits integres avec electrodes juxtaposees et circuit integre correspondant.
FR2679379B1 (fr) * 1991-07-16 1997-04-25 Thomson Composants Militaires Procede de fabrication de circuits integres avec electrodes tres etroites.
JP3116478B2 (ja) * 1991-10-29 2000-12-11 ソニー株式会社 半導体メモリ装置
US5696006A (en) * 1992-06-24 1997-12-09 Matsushita Electric Industrial Co., Ltd. Method of manufacturing Bi-MOS device
JP2847031B2 (ja) * 1993-05-03 1999-01-13 現代電子産業株式会社 半導体素子の配線製造方法
US6730549B1 (en) 1993-06-25 2004-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation
JPH0766424A (ja) * 1993-08-20 1995-03-10 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
KR0130376B1 (ko) * 1994-02-01 1998-04-06 문정환 반도체소자 제조방법
US6706572B1 (en) 1994-08-31 2004-03-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a thin film transistor using a high pressure oxidation step
KR0158065B1 (ko) * 1995-05-29 1998-12-01 스기야마 가즈히코 반도체 집적회로장치 및 그 제조방법
US6001676A (en) * 1995-05-29 1999-12-14 Matsushita Electronics Corporation Semiconductor integrated circuit apparatus and associated fabrication
JP3329640B2 (ja) * 1995-10-10 2002-09-30 株式会社東芝 半導体装置の製造方法
JP3562611B2 (ja) * 1996-11-05 2004-09-08 ソニー株式会社 半導体装置及びその製造方法
FR2756101B1 (fr) * 1996-11-19 1999-02-12 Sgs Thomson Microelectronics Procede de fabrication d'un transistor npn dans une technologie bicmos
FR2756100B1 (fr) 1996-11-19 1999-02-12 Sgs Thomson Microelectronics Transistor bipolaire a emetteur inhomogene dans un circuit integre bicmos
FR2756103B1 (fr) * 1996-11-19 1999-05-14 Sgs Thomson Microelectronics Fabrication de circuits integres bipolaires/cmos et d'un condensateur
FR2756104B1 (fr) * 1996-11-19 1999-01-29 Sgs Thomson Microelectronics Fabrication de circuits integres bipolaires/cmos
US6121101A (en) * 1998-03-12 2000-09-19 Lucent Technologies Inc. Process for fabricating bipolar and BiCMOS devices
US6274448B1 (en) * 1998-12-08 2001-08-14 United Microelectronics Corp. Method of suppressing junction capacitance of source/drain regions
JP3223895B2 (ja) 1998-12-15 2001-10-29 日本電気株式会社 半導体装置の製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4727038A (en) * 1984-08-22 1988-02-23 Mitsubishi Denki Kabushiki Kaisha Method of fabricating semiconductor device
FR2581248B1 (fr) * 1985-04-26 1987-05-29 Efcis Procede de fabrication de transistors a effet de champ et transistors bipolaires lateraux sur un meme substrat
JPH0622238B2 (ja) * 1985-10-02 1994-03-23 沖電気工業株式会社 バイポ−ラ型半導体集積回路装置の製造方法
US4737472A (en) * 1985-12-17 1988-04-12 Siemens Aktiengesellschaft Process for the simultaneous production of self-aligned bipolar transistors and complementary MOS transistors on a common silicon substrate
ATE94688T1 (de) * 1986-07-04 1993-10-15 Siemens Ag Integrierte bipolar- und komplementaere mostransistoren auf einem gemeinsamen substrat enthaltende schaltung und verfahren zu ihrer herstellung.
JPS63261746A (ja) * 1987-04-20 1988-10-28 Oki Electric Ind Co Ltd バイポ−ラ型半導体集積回路装置の製造方法
JPS63281456A (ja) * 1987-05-13 1988-11-17 Hitachi Ltd 半導体集積回路装置及びその製造方法
JPH01140761A (ja) * 1987-11-27 1989-06-01 Nec Corp 半導体装置
DE68921995T2 (de) * 1988-01-19 1995-12-07 Nat Semiconductor Corp Verfahren zum Herstellen eines Polysiliciumemitters und eines Polysiliciumgates durch gleichzeitiges Ätzen von Polysilicium auf einem dünnen Gateoxid.
JPH0744186B2 (ja) * 1989-03-13 1995-05-15 株式会社東芝 半導体装置の製造方法

Also Published As

Publication number Publication date
KR910013577A (ko) 1991-08-08
EP0435257A3 (en) 1991-10-09
DE69020708T2 (de) 1996-03-14
JPH03198371A (ja) 1991-08-29
US5100815A (en) 1992-03-31
KR0152078B1 (ko) 1998-10-01
EP0435257A2 (de) 1991-07-03
EP0435257B1 (de) 1995-07-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee