DE69015681D1 - Integrierte Gattermatrixhalbleiterschaltung. - Google Patents

Integrierte Gattermatrixhalbleiterschaltung.

Info

Publication number
DE69015681D1
DE69015681D1 DE69015681T DE69015681T DE69015681D1 DE 69015681 D1 DE69015681 D1 DE 69015681D1 DE 69015681 T DE69015681 T DE 69015681T DE 69015681 T DE69015681 T DE 69015681T DE 69015681 D1 DE69015681 D1 DE 69015681D1
Authority
DE
Germany
Prior art keywords
semiconductor circuit
integrated gate
gate matrix
matrix semiconductor
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69015681T
Other languages
English (en)
Other versions
DE69015681T2 (de
Inventor
Hiroyuki Hara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69015681D1 publication Critical patent/DE69015681D1/de
Application granted granted Critical
Publication of DE69015681T2 publication Critical patent/DE69015681T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118Masterslice integrated circuits
    • H01L27/11898Input and output buffer/driver structures
DE69015681T 1989-04-26 1990-04-26 Integrierte Gattermatrixhalbleiterschaltung. Expired - Fee Related DE69015681T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1106530A JP2509696B2 (ja) 1989-04-26 1989-04-26 ゲ―トアレ―半導体集積回路装置

Publications (2)

Publication Number Publication Date
DE69015681D1 true DE69015681D1 (de) 1995-02-16
DE69015681T2 DE69015681T2 (de) 1995-06-14

Family

ID=14435947

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69015681T Expired - Fee Related DE69015681T2 (de) 1989-04-26 1990-04-26 Integrierte Gattermatrixhalbleiterschaltung.

Country Status (5)

Country Link
US (1) US5039884A (de)
EP (1) EP0395070B1 (de)
JP (1) JP2509696B2 (de)
KR (1) KR930003455B1 (de)
DE (1) DE69015681T2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5122686A (en) * 1991-07-18 1992-06-16 Advanced Micro Devices, Inc. Power reduction design for ECL outputs that is independent of random termination voltage
US5341018A (en) * 1991-09-18 1994-08-23 Nec Corporation Semiconductor integrated circuit device having a plurality of input circuits each including differently sized transistors
US5581279A (en) * 1991-12-23 1996-12-03 Cirrus Logic, Inc. VGA controller circuitry

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3382727D1 (de) * 1982-06-30 1994-01-27 Fujitsu Ltd Integrierte Halbleiterschaltungsanordnung.
JPH0683049B2 (ja) * 1983-08-31 1994-10-19 株式会社日立製作所 半導体集積回路装置
JPS6074455A (ja) * 1983-09-29 1985-04-26 Fujitsu Ltd マスタスライス集積回路
US4623802A (en) * 1984-05-17 1986-11-18 Fairchild Semiconductor Corporation Multiple-stage gate network having independent reference voltage sources
US4631427A (en) * 1984-11-19 1986-12-23 Advanced Micro Devices, Inc. ECL gate circuit having internally generated reference voltages
JPS61188960A (ja) * 1985-02-18 1986-08-22 Fujitsu Ltd 半導体集積回路装置
US4751406A (en) * 1985-05-03 1988-06-14 Advanced Micro Devices, Inc. ECL circuit with output transistor auxiliary biasing circuit
US4933576A (en) * 1988-05-13 1990-06-12 Fujitsu Limited Gate array device having macro cells for forming master and slave cells of master-slave flip-flop circuit
JPH01289138A (ja) * 1988-05-16 1989-11-21 Toshiba Corp マスタースライス型半導体集積回路

Also Published As

Publication number Publication date
KR930003455B1 (ko) 1993-04-29
JPH02285657A (ja) 1990-11-22
EP0395070B1 (de) 1995-01-04
EP0395070A2 (de) 1990-10-31
KR900017178A (ko) 1990-11-15
JP2509696B2 (ja) 1996-06-26
US5039884A (en) 1991-08-13
DE69015681T2 (de) 1995-06-14
EP0395070A3 (de) 1991-06-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee