DE68927946D1 - Verfahren und Vorrichtung für die Synchronisierung von parallelen Prozessoren unter Verwendung einer unscharf definierten Sperre - Google Patents

Verfahren und Vorrichtung für die Synchronisierung von parallelen Prozessoren unter Verwendung einer unscharf definierten Sperre

Info

Publication number
DE68927946D1
DE68927946D1 DE68927946T DE68927946T DE68927946D1 DE 68927946 D1 DE68927946 D1 DE 68927946D1 DE 68927946 T DE68927946 T DE 68927946T DE 68927946 T DE68927946 T DE 68927946T DE 68927946 D1 DE68927946 D1 DE 68927946D1
Authority
DE
Germany
Prior art keywords
unsharp
lock
parallel processors
synchronizing parallel
synchronizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE68927946T
Other languages
English (en)
Other versions
DE68927946T2 (de
Inventor
Rajiv Gupta
Michael Abraham Epstein
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics NV filed Critical Philips Electronics NV
Publication of DE68927946D1 publication Critical patent/DE68927946D1/de
Application granted granted Critical
Publication of DE68927946T2 publication Critical patent/DE68927946T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/458—Synchronisation, e.g. post-wait, barriers, locks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Multi Processors (AREA)
DE68927946T 1988-08-02 1989-07-27 Verfahren und Vorrichtung für die Synchronisierung von parallelen Prozessoren unter Verwendung einer unscharf definierten Sperre Expired - Lifetime DE68927946T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US22727688A 1988-08-02 1988-08-02

Publications (2)

Publication Number Publication Date
DE68927946D1 true DE68927946D1 (de) 1997-05-15
DE68927946T2 DE68927946T2 (de) 1997-10-16

Family

ID=22852477

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68927946T Expired - Lifetime DE68927946T2 (de) 1988-08-02 1989-07-27 Verfahren und Vorrichtung für die Synchronisierung von parallelen Prozessoren unter Verwendung einer unscharf definierten Sperre

Country Status (4)

Country Link
US (2) US5802374A (de)
EP (1) EP0353819B1 (de)
JP (1) JP2947356B2 (de)
DE (1) DE68927946T2 (de)

Families Citing this family (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4019040A1 (de) * 1990-06-14 1991-12-19 Philips Patentverwaltung Multirechnersystem
JPH04184556A (ja) * 1990-11-20 1992-07-01 Mitsubishi Electric Corp 多重処理システムおよび多重処理システムの同期制御方法
US5434995A (en) * 1993-12-10 1995-07-18 Cray Research, Inc. Barrier synchronization for distributed memory massively parallel processing systems
US5721921A (en) * 1995-05-25 1998-02-24 Cray Research, Inc. Barrier and eureka synchronization architecture for multiprocessors
JP3573546B2 (ja) * 1995-10-27 2004-10-06 富士通株式会社 並列計算機における並列プロセススケジューリング方法および並列計算機用処理装置
US6055618A (en) * 1995-10-31 2000-04-25 Cray Research, Inc. Virtual maintenance network in multiprocessing system having a non-flow controlled virtual maintenance channel
US5864738A (en) * 1996-03-13 1999-01-26 Cray Research, Inc. Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller
JP2882475B2 (ja) * 1996-07-12 1999-04-12 日本電気株式会社 スレッド実行方法
EP0825506B1 (de) 1996-08-20 2013-03-06 Invensys Systems, Inc. Verfahren und Gerät zur Fernprozesssteuerung
JPH10149285A (ja) * 1996-11-18 1998-06-02 Hitachi Ltd 命令実行制御方法および情報処理装置
US6295601B1 (en) * 1997-05-30 2001-09-25 Sun Micro Systems, Inc. System and method using partial trap barrier instruction to provide trap barrier class-based selective stall of instruction processing pipeline
US6044206A (en) * 1997-10-14 2000-03-28 C-Cube Microsystems Out of order instruction processing using dual memory banks
US5970232A (en) * 1997-11-17 1999-10-19 Cray Research, Inc. Router table lookup mechanism
US6230252B1 (en) 1997-11-17 2001-05-08 Silicon Graphics, Inc. Hybrid hypercube/torus architecture
US6101181A (en) * 1997-11-17 2000-08-08 Cray Research Inc. Virtual channel assignment in large torus systems
JPH11259437A (ja) * 1998-03-12 1999-09-24 Hitachi Ltd 不要バリア命令の削減方式
US6216174B1 (en) 1998-09-29 2001-04-10 Silicon Graphics, Inc. System and method for fast barrier synchronization
JP2000132529A (ja) * 1998-10-23 2000-05-12 Sony Corp 並列処理装置、並列処理方法および記録媒体
AU5273100A (en) 1999-05-17 2000-12-05 Foxboro Company, The Methods and apparatus for control configuration with versioning, security, composite blocks, edit selection, object swapping, formulaic values and other aspects
US7089530B1 (en) 1999-05-17 2006-08-08 Invensys Systems, Inc. Process control configuration system with connection validation and configuration
US7043728B1 (en) 1999-06-08 2006-05-09 Invensys Systems, Inc. Methods and apparatus for fault-detecting and fault-tolerant process control
US6788980B1 (en) 1999-06-11 2004-09-07 Invensys Systems, Inc. Methods and apparatus for control using control devices that provide a virtual machine environment and that communicate via an IP network
US6438747B1 (en) * 1999-08-20 2002-08-20 Hewlett-Packard Company Programmatic iteration scheduling for parallel processors
US6374403B1 (en) * 1999-08-20 2002-04-16 Hewlett-Packard Company Programmatic method for reducing cost of control in parallel processes
US6507947B1 (en) * 1999-08-20 2003-01-14 Hewlett-Packard Company Programmatic synthesis of processor element arrays
US6751698B1 (en) 1999-09-29 2004-06-15 Silicon Graphics, Inc. Multiprocessor node controller circuit and method
US6674720B1 (en) 1999-09-29 2004-01-06 Silicon Graphics, Inc. Age-based network arbitration system and method
US6473660B1 (en) 1999-12-03 2002-10-29 The Foxboro Company Process control system and method with automatic fault avoidance
US6766437B1 (en) * 2000-02-28 2004-07-20 International Business Machines Corporation Composite uniprocessor
US6963967B1 (en) * 2000-06-06 2005-11-08 International Business Machines Corporation System and method for enabling weak consistent storage advantage to a firmly consistent storage architecture
US8949468B2 (en) 2001-09-21 2015-02-03 International Business Machines Corporation Method and system for time synchronization among systems using parallel sysplex links
US7346898B2 (en) * 2002-01-29 2008-03-18 Texas Instruments Incorporated Method for scheduling processors and coprocessors with bit-masking
JP2004088505A (ja) * 2002-08-27 2004-03-18 Matsushita Electric Ind Co Ltd 並列ストリーム暗復号装置及びその方法並びに並列ストリーム暗復号プログラム
US7577816B2 (en) 2003-08-18 2009-08-18 Cray Inc. Remote translation mechanism for a multinode system
US7379424B1 (en) 2003-08-18 2008-05-27 Cray Inc. Systems and methods for routing packets in multiprocessor computer systems
US7334110B1 (en) 2003-08-18 2008-02-19 Cray Inc. Decoupled scalar/vector computer architecture system and method
US7735088B1 (en) 2003-08-18 2010-06-08 Cray Inc. Scheduling synchronization of programs running as streams on multiple processors
US7743223B2 (en) 2003-08-18 2010-06-22 Cray Inc. Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system
US7421565B1 (en) 2003-08-18 2008-09-02 Cray Inc. Method and apparatus for indirectly addressed vector load-add -store across multi-processors
US7366873B1 (en) 2003-08-18 2008-04-29 Cray, Inc. Indirectly addressed vector load-operate-store method and apparatus
US7437521B1 (en) 2003-08-18 2008-10-14 Cray Inc. Multistream processing memory-and barrier-synchronization method and apparatus
US8307194B1 (en) 2003-08-18 2012-11-06 Cray Inc. Relaxed memory consistency model
US7761923B2 (en) 2004-03-01 2010-07-20 Invensys Systems, Inc. Process control methods and apparatus for intrusion detection, protection and network hardening
US7477255B1 (en) * 2004-04-12 2009-01-13 Nvidia Corporation System and method for synchronizing divergent samples in a programmable graphics processing unit
US7324112B1 (en) 2004-04-12 2008-01-29 Nvidia Corporation System and method for processing divergent samples in a programmable graphics processing unit
JP4749431B2 (ja) * 2005-03-04 2011-08-17 ヒューレット−パッカード デベロップメント カンパニー エル．ピー． パイプラインスループットを促進するための方法及び装置
US7478769B1 (en) 2005-03-09 2009-01-20 Cray Inc. Method and apparatus for cooling electronic components
US8392900B1 (en) * 2005-03-17 2013-03-05 Hewlett-Packard Development Company, L.P. Methods and systems for barrier reduction in parallel processing systems
JP4372043B2 (ja) * 2005-05-12 2009-11-25 株式会社ソニー・コンピュータエンタテインメント コマンド実行制御装置、コマンド実行指示装置およびコマンド実行制御方法
US7770170B2 (en) * 2005-07-12 2010-08-03 Microsoft Corporation Blocking local sense synchronization barrier
GB0524720D0 (en) * 2005-12-05 2006-01-11 Imec Inter Uni Micro Electr Ultra low power ASIP architecture II
US7860857B2 (en) 2006-03-30 2010-12-28 Invensys Systems, Inc. Digital data processing apparatus and methods for improving plant performance
US20080005357A1 (en) * 2006-06-30 2008-01-03 Microsoft Corporation Synchronizing dataflow computations, particularly in multi-processor setting
GB0613289D0 (en) * 2006-07-04 2006-08-16 Imagination Tech Ltd Synchronisation of execution threads on a multi-threaded processor
JP2008097498A (ja) * 2006-10-16 2008-04-24 Olympus Corp プロセッシング・エレメント、コントロール・ユニット、及びこれらを備える処理システム、分散処理方法
US8108845B2 (en) * 2007-02-14 2012-01-31 The Mathworks, Inc. Parallel programming computing system to dynamically allocate program portions
US7865778B2 (en) * 2007-02-20 2011-01-04 International Business Machines Corporation Method and system for detecting synchronization errors in programs
WO2009155483A1 (en) 2008-06-20 2009-12-23 Invensys Systems, Inc. Systems and methods for immersive interaction with actual and/or simulated facilities for process, environmental and industrial control
JP2010033555A (ja) * 2008-06-30 2010-02-12 Olympus Corp コントロール・ユニット、分散処理システム及び分散処理方法
US20100281469A1 (en) * 2009-04-30 2010-11-04 Nec Laboratories America, Inc. Symbolic predictive analysis for concurrent programs
US8127060B2 (en) 2009-05-29 2012-02-28 Invensys Systems, Inc Methods and apparatus for control configuration with control objects that are fieldbus protocol-aware
US8463964B2 (en) 2009-05-29 2013-06-11 Invensys Systems, Inc. Methods and apparatus for control configuration with enhanced change-tracking
US9959572B2 (en) 2009-12-10 2018-05-01 Royal Bank Of Canada Coordinated processing of data by networked computing resources
US9979589B2 (en) 2009-12-10 2018-05-22 Royal Bank Of Canada Coordinated processing of data by networked computing resources
EP2510451B1 (de) 2009-12-10 2019-08-28 Royal Bank Of Canada Synchronisierte datenverarbeitung über vernetzte computerressourcen
US9940670B2 (en) 2009-12-10 2018-04-10 Royal Bank Of Canada Synchronized processing of data by networked computing resources
US10057333B2 (en) 2009-12-10 2018-08-21 Royal Bank Of Canada Coordinated processing of data by networked computing resources
US9952620B2 (en) * 2014-04-10 2018-04-24 Intel Corporation Time-synchronizing a group of nodes
DE102017209697A1 (de) * 2016-06-13 2017-12-14 Denso Corporation Parallelisierungsverfahren, Parallelisierungswerkzeug und fahrzeuginterne Vorrichtung

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4295193A (en) * 1979-06-29 1981-10-13 International Business Machines Corporation Machine for multiple instruction execution
US4412303A (en) * 1979-11-26 1983-10-25 Burroughs Corporation Array processor architecture
JPS6043535B2 (ja) * 1979-12-29 1985-09-28 富士通株式会社 情報処理装置
US4435758A (en) * 1980-03-10 1984-03-06 International Business Machines Corporation Method for conditional branch execution in SIMD vector processors
US4468736A (en) * 1982-06-08 1984-08-28 Burroughs Corporation Mechanism for creating dependency free code for multiple processing elements
US4667290A (en) * 1984-09-10 1987-05-19 501 Philon, Inc. Compilers using a universal intermediate language
JPS6224366A (ja) * 1985-07-03 1987-02-02 Hitachi Ltd ベクトル処理装置
US5021945A (en) * 1985-10-31 1991-06-04 Mcc Development, Ltd. Parallel processor system for processing natural concurrencies and method therefor
JPS6337431A (ja) * 1986-08-01 1988-02-18 Hitachi Ltd 並列処理制御方法
JPH0795274B2 (ja) * 1986-09-19 1995-10-11 株式会社日立製作所 配列添字解析方法
JPH0814817B2 (ja) * 1986-10-09 1996-02-14 株式会社日立製作所 自動ベクトル化方法
US4965724A (en) * 1987-03-05 1990-10-23 Oki Electric Industry Co., Ltd. Compiler system using reordering of microoperations to eliminate interlocked instructions for pipelined processing of assembler source program
JPH01108638A (ja) * 1987-10-21 1989-04-25 Hitachi Ltd 並列化コンパイル方式
JP2738692B2 (ja) * 1988-01-29 1998-04-08 株式会社日立製作所 並列化コンパイル方法
US4989131A (en) * 1988-07-26 1991-01-29 International Business Machines Corporation Technique for parallel synchronization
JPH0630094B2 (ja) * 1989-03-13 1994-04-20 インターナショナル・ビジネス・マシーンズ・コーポレイション マルチプロセツサ・システム
US5127092A (en) * 1989-06-15 1992-06-30 North American Philips Corp. Apparatus and method for collective branching in a multiple instruction stream multiprocessor where any of the parallel processors is scheduled to evaluate the branching condition
US5317734A (en) * 1989-08-29 1994-05-31 North American Philips Corporation Method of synchronizing parallel processors employing channels and compiling method minimizing cross-processor data dependencies
JPH03119416A (ja) * 1989-10-03 1991-05-21 Toshiba Corp コンピュータシステム
US5119495A (en) * 1989-12-21 1992-06-02 Bull Hn Information Systems Inc. Minimizing hardware pipeline breaks using software scheduling techniques during compilation
JPH04211830A (ja) * 1990-02-05 1992-08-03 Matsushita Electric Ind Co Ltd 並列化コンパイル方式
US5261067A (en) * 1990-04-17 1993-11-09 North American Philips Corp. Method and apparatus for providing synchronized data cache operation for processors in a parallel processing system
JP3032031B2 (ja) * 1991-04-05 2000-04-10 株式会社東芝 ループ最適化方法及び装置
US5434995A (en) * 1993-12-10 1995-07-18 Cray Research, Inc. Barrier synchronization for distributed memory massively parallel processing systems

Also Published As

Publication number Publication date
JPH02110763A (ja) 1990-04-23
JP2947356B2 (ja) 1999-09-13
US5802374A (en) 1998-09-01
EP0353819A3 (de) 1991-07-17
EP0353819B1 (de) 1997-04-09
DE68927946T2 (de) 1997-10-16
US5787272A (en) 1998-07-28
EP0353819A2 (de) 1990-02-07

Similar Documents

Publication Publication Date Title
DE68927946D1 (de) Verfahren und Vorrichtung für die Synchronisierung von parallelen Prozessoren unter Verwendung einer unscharf definierten Sperre
DE3578645D1 (de) Verfahren und vorrichtung zur synchronisierung der taktuntersysteme von physikalischen modulen eines lokalen netzwerkes.
DE68915801D1 (de) Vorrichtung und Verfahren zur Verwendung einer Plattiermaske.
DE3853274D1 (de) Verfahren und Vorrichtung zur Aufteilung von Datenverarbeitungsfunktionen zwischen mehreren Prozessoren.
DE3575620D1 (de) Verfahren und vorrichtung zur warteschlangenverwaltung.
DE3485316D1 (de) Verfahren und vorrichtung zur darstellung einer kurve gleichmaessiger breite.
DE68908809D1 (de) Verfahren und vorrichtung zur führung einer notevakuierung.
DE69032635D1 (de) Verfahren und Vorrichtung zur Erkennung von Betriebsmittelkonflikten in einer Pipeline-Verarbeitungseinheit
DE68927413D1 (de) Verfahren und Vorrichtung zur Datenbankverarbeitung
DE3751981D1 (de) Verfahren und Vorrichtung zur Gewinnung von Strahlungsbildern unter Verwendung eines Licht-Pufferspeichers
DE68923877D1 (de) Verfahren und vorrichtung für die hydroponkultur.
DE69032812D1 (de) Vorrichtung und Verfahren zur parallelen Verarbeitung
DE68908850D1 (de) Verfahren und Vorrichtung für die Elektrolyse von Wasser.
DE3883701D1 (de) Verfahren und Vorrichtung für multiplexierte Vektorquantifizierung.
DE69024636D1 (de) Verfahren und apparatur für sequentielle mikrobielle anreicherung in einer einzigen vorrichtung
DE69028190D1 (de) Verfahren und Vorrichtung zur Softwareüberwachung und -entwicklung
DE3854527D1 (de) Vorrichtung und verfahren zur beschichtung von fixierungselementen.
DE3851514D1 (de) Verfahren und Vorrichtung zur überprüfung der Zustände einer Maschine.
DE69015074D1 (de) Verfahren und Vorrichtung zur Durchführung einer Fermentation.
DE69110596D1 (de) Verfahren und Vorrichtung zum Betätigen einer elektronischen Vorrichtung.
DE3862728D1 (de) Verfahren und vorrichtung zur behebung von stoerungen an arbeitsstellen einer textilmaschine.
DE3771764D1 (de) Verfahren und vorrichtung zur abscheidung von komponenten aus einer suspension.
DE58907018D1 (de) Vorrichtung und verfahren zum automatischen verbinden von fäden.
DE3764295D1 (de) Verfahren und vorrichtung zur pruefung von faeden.
DE3582796D1 (de) Verfahren und vorrichtung zur behandlung von werkstuecken mit verwendung einer sandstrahleinheit.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N

8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN

8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL