DE68923759D1 - Struktur und Prozess zur Herstellung einer Speicherzelle mit komplementären, senkrechten Transistoren. - Google Patents

Struktur und Prozess zur Herstellung einer Speicherzelle mit komplementären, senkrechten Transistoren.

Info

Publication number
DE68923759D1
DE68923759D1 DE68923759T DE68923759T DE68923759D1 DE 68923759 D1 DE68923759 D1 DE 68923759D1 DE 68923759 T DE68923759 T DE 68923759T DE 68923759 T DE68923759 T DE 68923759T DE 68923759 D1 DE68923759 D1 DE 68923759D1
Authority
DE
Germany
Prior art keywords
complementary
manufacturing
memory cell
vertical transistors
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68923759T
Other languages
English (en)
Other versions
DE68923759T2 (de
Inventor
Chakrapani Gajanan Jambotkar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE68923759D1 publication Critical patent/DE68923759D1/de
Publication of DE68923759T2 publication Critical patent/DE68923759T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
    • H01L27/0826—Combination of vertical complementary transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/10—SRAM devices comprising bipolar components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/011—Bipolar transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/072—Heterojunctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/087—I2L integrated injection logic
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/109—Memory devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
DE68923759T 1988-10-31 1989-10-10 Struktur und Prozess zur Herstellung einer Speicherzelle mit komplementären, senkrechten Transistoren. Expired - Fee Related DE68923759T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/265,062 US4981807A (en) 1988-10-31 1988-10-31 Process for fabricating complementary vertical transistor memory cell

Publications (2)

Publication Number Publication Date
DE68923759D1 true DE68923759D1 (de) 1995-09-14
DE68923759T2 DE68923759T2 (de) 1996-04-18

Family

ID=23008797

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68923759T Expired - Fee Related DE68923759T2 (de) 1988-10-31 1989-10-10 Struktur und Prozess zur Herstellung einer Speicherzelle mit komplementären, senkrechten Transistoren.

Country Status (6)

Country Link
US (1) US4981807A (de)
EP (1) EP0367708B1 (de)
JP (1) JPH0650764B2 (de)
BR (1) BR8905540A (de)
CA (1) CA1291577C (de)
DE (1) DE68923759T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5097312A (en) * 1989-02-16 1992-03-17 Texas Instruments Incorporated Heterojunction bipolar transistor and integration of same with field effect device
US5223449A (en) * 1989-02-16 1993-06-29 Morris Francis J Method of making an integrated circuit composed of group III-V compound field effect and bipolar semiconductors
JPH04261026A (ja) * 1991-01-08 1992-09-17 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5166083A (en) * 1991-03-28 1992-11-24 Texas Instruments Incorporated Method of integrating heterojunction bipolar transistors with heterojunction FETs and PIN diodes
US5213987A (en) * 1991-03-28 1993-05-25 Texas Instruments Incorporated Method of integrating heterojunction bipolar transistors with PIN diodes
US5268315A (en) * 1992-09-04 1993-12-07 Tektronix, Inc. Implant-free heterojunction bioplar transistor integrated circuit process
US5994727A (en) * 1997-09-30 1999-11-30 Samsung Electronics Co., Ltd. High performance gaas field effect transistor structure
DE60218685T2 (de) * 2002-10-08 2007-11-15 Stmicroelectronics S.R.L., Agrate Brianza Herstellungsverfahren für Zellenanordnung mit bipolaren Auswahltransistoren und zugehörige Zellenanordnung
EP1408550B1 (de) * 2002-10-08 2006-12-27 STMicroelectronics S.r.l. Zellenanordnung mit Bipolar-Auswahl-Transistor und Herstellungsverfahren
US9264027B1 (en) * 2013-03-14 2016-02-16 Integrated Device Technology, Inc. Process compensated delay

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS549279B2 (de) * 1972-07-12 1979-04-23
US4122482A (en) * 1973-02-02 1978-10-24 U.S. Philips Corporation Vertical complementary bipolar transistor device with epitaxial base zones
US4274891A (en) * 1979-06-29 1981-06-23 International Business Machines Corporation Method of fabricating buried injector memory cell formed from vertical complementary bipolar transistor circuits utilizing mono-poly deposition
US4485552A (en) * 1980-01-18 1984-12-04 International Business Machines Corporation Complementary transistor structure and method for manufacture
US4483726A (en) * 1981-06-30 1984-11-20 International Business Machines Corporation Double self-aligned fabrication process for making a bipolar transistor structure having a small polysilicon-to-extrinsic base contact area
US4573064A (en) * 1981-11-02 1986-02-25 Texas Instruments Incorporated GaAs/GaAlAs Heterojunction bipolar integrated circuit devices
US4482906A (en) * 1982-06-30 1984-11-13 International Business Machines Corporation Gallium aluminum arsenide integrated circuit structure using germanium
US4593305A (en) * 1983-05-17 1986-06-03 Kabushiki Kaisha Toshiba Heterostructure bipolar transistor
US4617724A (en) * 1983-06-30 1986-10-21 Fujitsu Limited Process for fabricating heterojunction bipolar transistor with low base resistance
US4586071A (en) * 1984-05-11 1986-04-29 International Business Machines Corporation Heterostructure bipolar transistor
JPS60253283A (ja) * 1984-05-29 1985-12-13 Toshiba Corp 半導体発光素子
US4649411A (en) * 1984-12-17 1987-03-10 Motorola, Inc. Gallium arsenide bipolar ECL circuit structure
US4635087A (en) * 1984-12-28 1987-01-06 Motorola, Inc. Monolithic bipolar SCR memory cell
JPS6249658A (ja) * 1985-08-29 1987-03-04 Matsushita Electric Ind Co Ltd ヘテロ接合バイポ−ラトランジスタおよびその製造方法
US4771013A (en) * 1986-08-01 1988-09-13 Texas Instruments Incorporated Process of making a double heterojunction 3-D I2 L bipolar transistor with a Si/Ge superlattice
JPS63188969A (ja) * 1987-01-30 1988-08-04 Matsushita Electric Ind Co Ltd バイポ−ラトランジスタの製造方法
JP2587826B2 (ja) * 1987-03-27 1997-03-05 日本電信電話株式会社 バイポ−ラトランジスタとその製造方法
US4807008A (en) * 1987-09-14 1989-02-21 Rockwell International Corporation Static memory cell using a heterostructure complementary transistor switch

Also Published As

Publication number Publication date
EP0367708A1 (de) 1990-05-09
BR8905540A (pt) 1990-05-29
CA1291577C (en) 1991-10-29
DE68923759T2 (de) 1996-04-18
JPH0650764B2 (ja) 1994-06-29
US4981807A (en) 1991-01-01
EP0367708B1 (de) 1995-08-09
JPH02137362A (ja) 1990-05-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee