DE68921700D1 - Phasenverriegelungsschleife zum Ableiten eines Taktsignals in Datenübertragungsverbindungen mit Gigabit-Übertragungsraten. - Google Patents

Phasenverriegelungsschleife zum Ableiten eines Taktsignals in Datenübertragungsverbindungen mit Gigabit-Übertragungsraten.

Info

Publication number
DE68921700D1
DE68921700D1 DE68921700T DE68921700T DE68921700D1 DE 68921700 D1 DE68921700 D1 DE 68921700D1 DE 68921700 T DE68921700 T DE 68921700T DE 68921700 T DE68921700 T DE 68921700T DE 68921700 D1 DE68921700 D1 DE 68921700D1
Authority
DE
Germany
Prior art keywords
deriving
clock signal
phase lock
lock loop
data transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68921700T
Other languages
English (en)
Other versions
DE68921700T2 (de
Inventor
Craig Corsetto
Tom Hornak
Richard C Walker
Rasmus Nordby
Chu Yen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE68921700D1 publication Critical patent/DE68921700D1/de
Publication of DE68921700T2 publication Critical patent/DE68921700T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE68921700T 1988-11-18 1989-10-30 Phasenverriegelungsschleife zum Ableiten eines Taktsignals in Datenübertragungsverbindungen mit Gigabit-Übertragungsraten. Expired - Fee Related DE68921700T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/273,302 US4926447A (en) 1988-11-18 1988-11-18 Phase locked loop for clock extraction in gigabit rate data communication links

Publications (2)

Publication Number Publication Date
DE68921700D1 true DE68921700D1 (de) 1995-04-20
DE68921700T2 DE68921700T2 (de) 1995-07-27

Family

ID=23043373

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68921700T Expired - Fee Related DE68921700T2 (de) 1988-11-18 1989-10-30 Phasenverriegelungsschleife zum Ableiten eines Taktsignals in Datenübertragungsverbindungen mit Gigabit-Übertragungsraten.

Country Status (4)

Country Link
US (1) US4926447A (de)
EP (1) EP0369628B1 (de)
JP (1) JP2863763B2 (de)
DE (1) DE68921700T2 (de)

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5438621A (en) * 1988-11-02 1995-08-01 Hewlett-Packard Company DC-free line code and bit and frame synchronization for arbitrary data transmission
US5042052A (en) * 1990-02-16 1991-08-20 Harris Corporation Carrier acquisition scheme for QAM and QPSK data
JP3253298B2 (ja) * 1990-11-13 2002-02-04 アジレント・テクノロジーズ・インク 通信リンクを介した伝送用のデジタルビットストリームの符号化方法
US5136617A (en) * 1990-12-03 1992-08-04 At&T Bell Laboratories Switching technique for attaining synchronization
DE4307673A1 (de) * 1993-03-11 1994-09-15 Blaupunkt Werke Gmbh Schaltungsanordnung zur Erzeugung einer Abstimmspannung
SE501156C2 (sv) * 1993-04-21 1994-11-28 Ellemtel Utvecklings Ab Referenssignal sammansatt av klocksignal och synkroniseringssignal, anordning och förfarande för synkronisering m.h.a. referenssignal
US5757857A (en) * 1994-07-21 1998-05-26 The Regents Of The University Of California High speed self-adjusting clock recovery circuit with frequency detection
US5640523A (en) * 1994-09-02 1997-06-17 Cypress Semiconductor Corporation Method and apparatus for a pulsed tri-state phase detector for reduced jitter clock recovery
US5455540A (en) * 1994-10-26 1995-10-03 Cypress Semiconductor Corp. Modified bang-bang phase detector with ternary output
JP3467888B2 (ja) * 1995-02-08 2003-11-17 三菱電機株式会社 受信装置及び送受信装置
US5528638A (en) * 1995-05-24 1996-06-18 Sun Microsystems, Inc. Multiple phase shifted clocks generation using a minimal set of signals from a PLL
US5838749A (en) * 1995-06-05 1998-11-17 Broadband Communications Products, Inc. Method and apparatus for extracting an embedded clock from a digital data signal
US5963608A (en) * 1995-06-05 1999-10-05 Broadband Communications Products, Inc. Clock extractor for high speed, variable data rate communication system
US5999571A (en) * 1995-10-05 1999-12-07 Silicon Image, Inc. Transition-controlled digital encoding and signal transmission system
US5825824A (en) * 1995-10-05 1998-10-20 Silicon Image, Inc. DC-balanced and transition-controlled encoding method and apparatus
US5974464A (en) * 1995-10-06 1999-10-26 Silicon Image, Inc. System for high speed serial video signal transmission using DC-balanced coding
US5663991A (en) * 1996-03-08 1997-09-02 International Business Machines Corporation Integrated circuit chip having built-in self measurement for PLL jitter and phase error
US6081550A (en) * 1997-02-26 2000-06-27 Alcatel Method of testing clock paths and network elements for carrying out the method
US5987085A (en) * 1997-03-26 1999-11-16 Lsi Logic Coporation Clock recovery circuit
US6704382B1 (en) * 1997-07-11 2004-03-09 Tellabs Operations, Inc. Self-sweeping autolock PLL
JP3731313B2 (ja) * 1997-09-19 2006-01-05 ソニー株式会社 クロック再生回路およびデータ伝送装置
US5907253A (en) * 1997-11-24 1999-05-25 National Semiconductor Corporation Fractional-N phase-lock loop with delay line loop having self-calibrating fractional delay element
US6285722B1 (en) 1997-12-05 2001-09-04 Telcordia Technologies, Inc. Method and apparatus for variable bit rate clock recovery
US6192093B1 (en) * 1999-07-30 2001-02-20 Agilent Technologies Enhanced CIMT coding system and method with automatic word alignment for simplex operation
GB2357382B (en) * 1999-12-17 2004-03-31 Mitel Corp Clock recovery PLL
US6683930B1 (en) * 1999-12-23 2004-01-27 Cypress Semiconductor Corp. Digital phase/frequency detector, and clock generator and data recovery PLL containing the same
US6775345B1 (en) * 1999-12-30 2004-08-10 Intel Corporation Delay locked loop based data recovery circuit for data communication
US20020091885A1 (en) * 2000-12-30 2002-07-11 Norm Hendrickson Data de-skew method and system
US20020093986A1 (en) * 2000-12-30 2002-07-18 Norm Hendrickson Forward data de-skew method and system
US20020090045A1 (en) * 2001-01-10 2002-07-11 Norm Hendrickson Digital clock recovery system
WO2002062004A1 (en) 2001-02-01 2002-08-08 Vitesse Semiconductor Corporation Rz recovery
US7257183B2 (en) * 2001-07-10 2007-08-14 Rambus Inc. Digital clock recovery circuit
KR100432883B1 (ko) * 2001-12-18 2004-05-22 삼성전자주식회사 클럭 듀티/스큐 보정 기능을 갖는 위상 분주 회로
JP3850856B2 (ja) * 2002-05-17 2006-11-29 富士通株式会社 Ｐｌｏ装置
US7372928B1 (en) 2002-11-15 2008-05-13 Cypress Semiconductor Corporation Method and system of cycle slip framing in a deserializer
US8085857B1 (en) 2003-09-25 2011-12-27 Cypress Semiconductor Corporation Digital-compatible multi-state-sense input
US7227393B1 (en) * 2004-06-03 2007-06-05 Marvell International Ltd. Method and apparatus for adaptive delay cancellation in high-speed wireline transmitters
US7171321B2 (en) 2004-08-20 2007-01-30 Rambus Inc. Individual data line strobe-offset control in memory systems
US7543172B2 (en) 2004-12-21 2009-06-02 Rambus Inc. Strobe masking in a signaling system having multiple clock domains
US7688672B2 (en) * 2005-03-14 2010-03-30 Rambus Inc. Self-timed interface for strobe-based systems
US7221704B2 (en) 2005-08-01 2007-05-22 Marvell World Trade Ltd. All digital implementation of clock spectrum spreading (dither) for low power/die area
US7873132B2 (en) * 2005-09-21 2011-01-18 Hewlett-Packard Development Company, L.P. Clock recovery
US7920665B1 (en) 2005-09-28 2011-04-05 Cypress Semiconductor Corporation Symmetrical range controller circuit and method
US8121237B2 (en) 2006-03-16 2012-02-21 Rambus Inc. Signaling system with adaptive timing calibration
US7728675B1 (en) 2006-03-31 2010-06-01 Cypress Semiconductor Corporation Fast lock circuit for a phase lock loop
US7715512B2 (en) * 2006-09-26 2010-05-11 Advantest Corporation Jitter measurement apparatus, jitter measurement method, and recording medium
CN101232340B (zh) * 2007-01-23 2012-10-03 华为技术有限公司 通信系统、方法、发送装置以及接收装置
EP2220773B1 (de) * 2007-12-06 2012-09-05 Rambus Inc. Flankenbasierte signalverlusterkennung
US7576584B2 (en) * 2007-12-14 2009-08-18 Analog Devices, Inc. Clock generators for generation of in-phase and quadrature clock signals
KR100960118B1 (ko) * 2007-12-17 2010-05-27 한국전자통신연구원 클럭 지터 발생 장치 및 이를 포함하는 시험 장치
US8207765B2 (en) * 2009-07-20 2012-06-26 Advantest Corporation Signal generation apparatus and test apparatus
JP5670775B2 (ja) * 2011-02-07 2015-02-18 ルネサスエレクトロニクス株式会社 シリアル通信回路、シリアル通信制御方法および半導体集積回路装置
US9128643B2 (en) * 2012-05-17 2015-09-08 Silicon Motion Inc. Method and apparatus performing clock extraction utilizing edge analysis upon a training sequence equalization pattern
JP6027359B2 (ja) * 2012-07-24 2016-11-16 ラピスセミコンダクタ株式会社 クロックデータリカバリ回路及び半導体装置
JP6027358B2 (ja) * 2012-07-24 2016-11-16 ラピスセミコンダクタ株式会社 クロックデータリカバリ回路及び半導体装置
EP2755350A1 (de) * 2013-01-15 2014-07-16 Alcatel-Lucent Vorrichtung zur Ausführung von Takt- und/oder Daten-Rückgewinnung
FR3029661B1 (fr) * 2014-12-04 2016-12-09 Stmicroelectronics Rousset Procedes de transmission et de reception d'un signal binaire sur un lien serie, en particulier pour la detection de la vitesse de transmission, et dispositifs correspondants
CN108334469A (zh) * 2017-12-20 2018-07-27 广州晶序达电子科技有限公司 一种高速差分串行数据传输的方法、系统和装置
KR20210073299A (ko) * 2019-12-10 2021-06-18 삼성전자주식회사 클록 데이터 복원 회로 및 이를 포함하는 장치

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4280099A (en) * 1979-11-09 1981-07-21 Sperry Corporation Digital timing recovery system
US4400667A (en) * 1981-01-12 1983-08-23 Sangamo Weston, Inc. Phase tolerant bit synchronizer for digital signals
US4371974A (en) * 1981-02-25 1983-02-01 Rockwell International Corporation NRZ Data phase detector
GB2107142B (en) * 1981-10-07 1984-10-10 Marconi Co Ltd Frequency synthesisers
JPS5986333A (ja) * 1982-11-08 1984-05-18 Sanyo Electric Co Ltd クロツクパルス発生回路
US4743857A (en) * 1984-04-18 1988-05-10 Telex Computer Products, Inc. Digital/analog phase-locked oscillator
US4633488A (en) * 1984-11-13 1986-12-30 Digital Equipment Corporation Phase-locked loop for MFM data recording
US4782484A (en) * 1986-04-18 1988-11-01 Bell Communications Research, Inc. Encoding and decoding signals for transmission over a multi-access medium
US4847874A (en) * 1987-09-09 1989-07-11 Westinghouse Electric Corp. Clock recovery system for digital data

Also Published As

Publication number Publication date
DE68921700T2 (de) 1995-07-27
EP0369628A2 (de) 1990-05-23
JP2863763B2 (ja) 1999-03-03
EP0369628B1 (de) 1995-03-15
EP0369628A3 (de) 1991-10-09
JPH02192338A (ja) 1990-07-30
US4926447A (en) 1990-05-15

Similar Documents

Publication Publication Date Title
DE68921700D1 (de) Phasenverriegelungsschleife zum Ableiten eines Taktsignals in Datenübertragungsverbindungen mit Gigabit-Übertragungsraten.
DE68923520D1 (de) Schnalle mit rutschfestem Stab zum Einstellen eines Gurtes.
EP0502739A3 (en) Nrz clock and data recovery system employing phase lock loop
DE68900214D1 (de) Phasenverriegelte schleifenschaltung sowie bitdetektorschaltung mit einer derartigen phasenverriegelten schleifenschaltung.
FR2682792B1 (fr) Dispositif destine a eviter les carambolages en chaine.
DE69107248D1 (de) Sender mit einer elektronischen Anordnung zum Erzeugen eines modulierten Trägersignals.
DE69107247D1 (de) Elektronische Anordnung zum Empfangen eines modulierten Trägersignals.
DK683688D0 (da) Faselaasning af baudklokken i en datademodulator
DE68905835D1 (de) Geraet zur erzeugung eines videosignals, welches einen bereich mit raeumlich veraenderlicher faerbung darstellt.
DE3481595D1 (de) Registerregelung in geschlossener schleife.
AT399707B (de) Abnehmbarer verschluss für einen behälter
DE3852182D1 (de) Schnellwechselmechanismus mit exzentrischer sperrvorrichtung.
AR244407A1 (es) Una correa dentada flexible.
FR2555342B3 (fr) Marque applicable a des articles en general, pourvue d'un dispositif de verrouillage empechant son enlevement abusif
DE68922170D1 (de) Gerät zum Empfangen eines Digitalsignals.
DE68914547D1 (de) Träger mit kastenförmiger Struktur.
FR2616474B1 (fr) Dispositif de verrouillage a rattrapage automatique de jeu, notamment pour le verrouillage d'un panneau de fermeture
NO893443L (no) Fremgangsmaate for overvaakning og regulering av avleiringer i en broenn.
FR2653614B1 (fr) Boucle de verrouillage de phase avec commande a glissement de phase.
FR2652761B1 (fr) Concasseur giratoir pour roches muni d'un dispositif d'etancheite.
DE58904858D1 (de) Anordnung zur uberwachung eines taktsignals.
FR2601066B1 (fr) Dispositif d'entrainement pour machines d'exploitation minieres a chaine a fuseaux.
DE69010253D1 (de) Einrichtung zur Erzeugung eines Horizontalrückstellsignals, synchron mit einem hilfsträgerverriegelten Taktsignal.
DE69021432D1 (de) Schaltungsanordnung zum Liefern eines periodischen, im wesentlichen parabelförmigen Signals.
DE68924071D1 (de) Bestellungszufuhrverfahren für einen magnetisch kodierbaren film mit zugewiesenen spuren.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D.STAATES DELA

8339 Ceased/non-payment of the annual fee