DE60228856D1 - Verfahren zur Herstellung von Mikrokanälen in einer integretierten Struktur - Google Patents

Verfahren zur Herstellung von Mikrokanälen in einer integretierten Struktur

Info

Publication number
DE60228856D1
DE60228856D1 DE60228856T DE60228856T DE60228856D1 DE 60228856 D1 DE60228856 D1 DE 60228856D1 DE 60228856 T DE60228856 T DE 60228856T DE 60228856 T DE60228856 T DE 60228856T DE 60228856 D1 DE60228856 D1 DE 60228856D1
Authority
DE
Germany
Prior art keywords
integrated structure
microchannels
producing
producing microchannels
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60228856T
Other languages
English (en)
Inventor
Arrigo Giuseppe Alessio Maria D
Rosario Corrado Spinella
Giuseppe Arena
Simona Lorenti
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE60228856D1 publication Critical patent/DE60228856D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/005—Bulk micromachining
    • B81C1/00507—Formation of buried layers by techniques other than deposition, e.g. by deep implantation of elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76289—Lateral isolation by air gap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
    • G01N27/416—Systems
    • G01N27/447—Systems using electrophoresis

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Micromachines (AREA)
DE60228856T 2002-12-04 2002-12-04 Verfahren zur Herstellung von Mikrokanälen in einer integretierten Struktur Expired - Lifetime DE60228856D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02425746A EP1427011B1 (de) 2002-12-04 2002-12-04 Verfahren zur Herstellung von Mikrokanälen in einer integretierten Struktur

Publications (1)

Publication Number Publication Date
DE60228856D1 true DE60228856D1 (de) 2008-10-23

Family

ID=32309533

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60228856T Expired - Lifetime DE60228856D1 (de) 2002-12-04 2002-12-04 Verfahren zur Herstellung von Mikrokanälen in einer integretierten Struktur

Country Status (3)

Country Link
US (2) US7063798B2 (de)
EP (1) EP1427011B1 (de)
DE (1) DE60228856D1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8454513B2 (en) * 2004-12-30 2013-06-04 Stc.Unm Micro-machined medical devices, methods of fabricating microdevices, and methods of medical diagnosis, imaging, stimulation, and treatment
ITVA20050034A1 (it) * 2005-05-13 2006-11-14 St Microelectronics Srl Celle a combustibile realizzate in un singolo strato di silicio monocristallino e processo di fabbricazione
US7557002B2 (en) 2006-08-18 2009-07-07 Micron Technology, Inc. Methods of forming transistor devices
US7989322B2 (en) 2007-02-07 2011-08-02 Micron Technology, Inc. Methods of forming transistors
DE102008040597A1 (de) * 2008-07-22 2010-01-28 Robert Bosch Gmbh Mikromechanisches Bauelement mit Rückvolumen
IT1399354B1 (it) 2009-07-17 2013-04-16 Torino Politecnico Sistema a microcelle a combustibile e relativo metodo di fabbricazione
US20230037442A1 (en) 2019-12-17 2023-02-09 Ecole Polytechnique Federale De Lausanne (Epfl) Integrated electronic device with embedded microchannels and a method for producing thereof
WO2021237532A1 (zh) * 2020-05-27 2021-12-02 瑞声声学科技(深圳)有限公司 一种深腔刻蚀方法
CN111620297B (zh) * 2020-05-27 2023-02-28 瑞声声学科技(深圳)有限公司 一种深腔刻蚀方法
CN111901643B (zh) * 2020-06-20 2022-04-22 河北广电无线传媒有限公司 一种高可靠性iptv机顶盒

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4685198A (en) * 1985-07-25 1987-08-11 Matsushita Electric Industrial Co., Ltd. Method of manufacturing isolated semiconductor devices
US4993143A (en) * 1989-03-06 1991-02-19 Delco Electronics Corporation Method of making a semiconductive structure useful as a pressure sensor
US5429734A (en) * 1993-10-12 1995-07-04 Massachusetts Institute Of Technology Monolithic capillary electrophoretic device
JPH11204537A (ja) * 1998-01-14 1999-07-30 Toshiba Corp 半導体装置の製造方法
DE69930099T2 (de) * 1999-04-09 2006-08-31 Stmicroelectronics S.R.L., Agrate Brianza Herstellung von vergrabenen Hohlräumen in einer einkristallinen Halbleiterscheibe und Halbleiterscheibe
DE69935495T2 (de) * 1999-04-29 2007-11-29 Stmicroelectronics S.R.L., Agrate Brianza Herstellungsverfahren für vergrabene Kanäle und Hohlräume in Halbleiterscheiben
US6426254B2 (en) * 1999-06-09 2002-07-30 Infineon Technologies Ag Method for expanding trenches by an anisotropic wet etch
DE69937106T2 (de) * 1999-07-09 2008-06-05 Stmicroelectronics S.R.L., Agrate Brianza Verfahren zur Herstellung von Strukturen mit vergrabenen Oxidbereichen in einem Halbleitersubstrat
EP1073112A1 (de) * 1999-07-26 2001-01-31 STMicroelectronics S.r.l. Verfahren zur Herstellung eines SOI-Wafers mittels Oxidierung von vergrabenen Hohlräumen
US6833079B1 (en) * 2000-02-17 2004-12-21 Applied Materials Inc. Method of etching a shaped cavity
EP1130631A1 (de) * 2000-02-29 2001-09-05 STMicroelectronics S.r.l. Herstellungsverfahren eines vergrabenen Hohlraumes in einer Halbleiterscheibe
US6406982B2 (en) * 2000-06-05 2002-06-18 Denso Corporation Method of improving epitaxially-filled trench by smoothing trench prior to filling
AU2001297774A1 (en) * 2000-12-19 2002-10-28 Coventor, Incorporated Light transmissive substrate for an optical mems device
US6582987B2 (en) * 2000-12-30 2003-06-24 Electronics And Telecommunications Research Institute Method of fabricating microchannel array structure embedded in silicon substrate
DE10113187C1 (de) * 2001-03-19 2002-08-29 Infineon Technologies Ag Verfahren zur Herstellung eines Grabenkondensators einer Speicherzelle eines Halbleiterspeichers

Also Published As

Publication number Publication date
EP1427011B1 (de) 2008-09-10
US7063798B2 (en) 2006-06-20
US20060207972A1 (en) 2006-09-21
EP1427011A1 (de) 2004-06-09
US20040217447A1 (en) 2004-11-04

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