US20060207972A1 - Method for realizing microchannels in an integrated structure - Google Patents

Method for realizing microchannels in an integrated structure Download PDF

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US20060207972A1
US20060207972A1 US11439075 US43907506A US2006207972A1 US 20060207972 A1 US20060207972 A1 US 20060207972A1 US 11439075 US11439075 US 11439075 US 43907506 A US43907506 A US 43907506A US 2006207972 A1 US2006207972 A1 US 2006207972A1
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microchannel
substrate
monocrystalline silicon
trench
integrated structure
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US11439075
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Alessio D'arrigo Guiseppe
Rosario Spinella
Guiseppe Arena
Simona Lorenti
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STMicroelectronics SRL
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STMicroelectronics SRL
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/005Bulk micromachining
    • B81C1/00507Formation of buried layers by techniques other than deposition, e.g. by deep implantation of elements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • H01L21/30608Anisotropic liquid etching
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76289Lateral isolation by air gap
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/764Air gaps
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00Investigating or analysing materials by the use of electric, electro-chemical, or magnetic means
    • G01N27/26Investigating or analysing materials by the use of electric, electro-chemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
    • G01N27/416Systems
    • G01N27/447Systems using electrophoresis

Abstract

A process is presented for realizing buried microchannels in an integrated structure comprising a monocrystalline silicon substrate. The process forms in the substrate at least one trench. A microchannel is obtained starting from a small surface port of the trench by anisotropic etching of the trench. The microchannel is then completely buried in the substrate by growing a microcrystalline structure to enclose the small surface port.

Description

    CROSS REFERENCE TO RELATED APPLICATION
  • The present application is a Divisional Application of U.S. application for patent Ser. No. 10/726,264, filed Dec. 2, 2003, which claims priority from European Application for Patent No. 02425746.1 filed Dec. 4, 2002, the disclosures of which each being hereby incorporated by reference.
  • BACKGROUND OF THE INVENTION
  • 1. Technical Field of the Invention
  • The present invention relates to a process for realizing microchannels in an integrated structure. More specifically, the invention relates to a process for realizing microchannels buried in an integrated structure comprising a monocrystalline silicon substrate.
  • 2. Description of Related Art
  • Typical procedures for analyzing biological materials, such as nucleic acid, involve a variety of operations starting from raw material. These operations may include various degrees of cell purification, lysis, amplification or purification, and analysis of the resulting amplification or purification product.
  • As an example, in DNA-based blood tests the samples are often purified by filtration, centrifugation or by electrophoresis so as to eliminate all the non-nucleated cells. Then, the remaining white blood cells are lysed using chemical, thermal or biochemical means in order to liberate the DNA to be analyzed. Next, the DNA is denatured by thermal, biochemical or chemical processes and amplified by an amplification reaction, such as PCR (polymerase chain reaction), LCR (ligase chain reaction), SDA (strand displacement amplification), TMA (transcription-mediated amplification), RCA (rolling circle amplification), and the like. The amplification step allows the operator to avoid purification of the DNA being studied because the amplified product greatly exceeds the starting DNA in the sample.
  • The procedures are similar if RNA is to be analyzed, but more emphasis is placed on purification or other means to protect the labile RNA molecule. RNA is usually copied into DNA (cDNA) and then the analysis proceeds as described for DNA.
  • Finally, the amplification product undergoes some type of analysis, usually based on sequence or size or some combination thereof. In an analysis by hybridization, for example, the amplified DNA is passed over a plurality of detectors made up of individual oligonucleotide detector “probes” that are anchored, for example, on electrodes. If the amplified DNA strands are complementary to the probes, stable bonds will be formed between them and the hybridized detectors can be read by observation by a wide variety of means, including optical, electrical, magnetic, mechanical or thermal means.
  • Other biological molecules are analyzed in a similar way, but typically molecule purification is substituted for amplification and detection methods vary according to the molecule being detected. For example, a common diagnostic involves the detection of a specific protein by binding to its antibody or by a specific enzymatic reaction. Lipids, carbohydrates, drugs and small molecules from biological fluids are processed in similar ways. However, we have simplified the discussion herein by focusing on nucleic acid analysis, in particular DNA amplification, as an example of a biological molecule that can be analyzed using the devices of the invention.
  • The steps of nucleic acid analysis described above are currently performed using different devices, each of which presides over one aspect of the process. The use of separate devices increases cost and decreases the efficiency of sample processing because transfer time between devices is required, larger samples are required to accommodate sample loss and instrument size, and because qualified operators are required to avoid contamination problems. For these reasons an integrated microreactor would be preferred.
  • For performing treatment of fluids, integrated microreactors of semiconductor material are already known. Microchannel arrays are widely used in different systems such as medical systems for fluid administration, devices for biological use for manufacturing miniaturized microreactors, in electrophoresis processes, in DNA chip and other array applications, in integrated fuel cells, ink jet printers, and the like. Microchannels are used also, for example, for the refrigeration of devices located above microchannels.
  • One application of interest is the use of microchannels to make a miniaturized microreactor for diagnostic uses (see especially, U.S. Ser. No. 10/663,268 filed Sep. 16, 2003 and references cited therein, each which incorporated by reference in their entirety). A number of such devices are described for the amplification of nucleic acid, such as DNA or RNA, or for other biological tests, such as immunological detection of antigens in a biological sample. The microreactor can be combined with one or more integrated sample pretreatment chamber, micropump, heater, and also with integrated sample analysis features, such as an array of nucleic acid or antibody detectors. Such devices are described in more detail in U.S. Ser. No. 10/663,268, and related patents or applications.
  • However, complex procedures are traditionally required in order to form a microchannel system. In particular, conventional processes for forming embedded microchannels require so-called wafer bonding or opening structures from the backside of the wafer back.
  • A process for forming microchannels is described for example in the U.S. Pat. No. 6,376,291 granted on Apr. 23, 2002. In particular, this document describes a process for forming in a monocrystalline silicon body an etching-aid region for the monocrystalline silicon wherein a nucleus region is provided, surrounded by a protective structure and having a port extending along the whole etching-aid region.
  • According to the '291 patent, a polycrystalline layer is grown above the port in order to form a cavity completely embedded in the resulting wafer. Although advantageous from many aspects, the process described by the '291 patent is rather complex and it does not allow a completely crystalline final microstructure to be obtained.
  • The technical problem underlying the present invention is to provide a process for forming microchannels, having such structural and functional characteristics as to overcome the limits and drawbacks still affecting the processes according to the prior art.
  • SUMMARY OF THE INVENTION
  • The solution underlying the present invention is to use trench structures to obtain deep silicon cavities. A small surface port is used as a precursor for forming microchannels in an integrated structure. Through the port, a trench is defined and then etched to form the microchannel structure. The port is then closed by silicon to thus obtain a completely crystalline final structure.
  • In accordance with an embodiment of the invention, an integrated structure comprises at least a monocrystalline silicon substrate wherein at least one microchannel is formed which is nearly entirely buried inside said substrate.
  • In accordance with an embodiment of the invention, a fluid microchannel buried in an integrated structure comprising a monocrystalline silicon substrate comprises an anisotropically formed trench in said substrate, and a completely monocrystalline structure which closes a top of the anisotropically formed trench to define the fluid microchannel.
  • In accordance with another embodiment, an integrated structure fluid microchannel comprises an elongated trench formed in a monocrystalline silicon substrate and anisotropically etched to obtain a deep cavity characterized by an elongated surface port, and a closure of at least a portion of the elongated surface port of the elongated trench to define with the deep cavity in the silicon substrate a tunnel-like microchannel.
  • In accordance with another embodiment, an integrated structure microchannel comprises a narrow elongated trench formed in a monocrystalline silicon substrate and anisotropically wet etched to form a microchannel structure having a generally rhombohedral cross-sectional shape with a top port substrate surface opening, and a closure of the top port substrate surface opening of the microchannel structure to enclose the microchannel structure.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • A more complete understanding of the method and apparatus of the present invention may be acquired by reference to the following Detailed Description when taken in conjunction with the accompanying Drawings wherein:
  • FIG. 1 schematically shows a section of an integrated structure with at least a microchannel realized with the process according to the invention;
  • FIGS. 2, 3A, 3B and 4 are micrographs of the integrated structure of FIG. 1 in different steps of the process according to the invention;
  • FIG. 5 schematically shows an integrated structure with microchannels realized according to an alternative embodiment of the process according to the invention;
  • FIGS. 6A-6F schematically show an integrated structure with microchannels in different steps of a further alternative embodiment of the process according to the invention; and
  • FIGS. 7A and 7B show micrographs of the final integrated structure with microchannels realized with the process according to the invention.
  • DETAILED DESCRIPTION OF THE DRAWINGS
  • The invention relates particularly, but not exclusively, to a process for realizing miniaturized microchannels buried in a completely monocrystalline array and the following description is made with reference to this field of application for convenience of illustration only.
  • With reference to the drawings, and particularly to FIG. 1, an integrated structure comprising a plurality of microchannels 10 formed according to the invention is globally and schematically indicated with reference 1.
  • In particular, the integrated structure 1 comprises a monocrystalline silicon substrate 2 whereon a monocrystalline silicon layer 3 is grown.
  • The monocrystalline silicon layer 3 is obtained in turn by epitaxial growth on convenient cavities (rhombohedral in the example shown) of said microchannels 10 without using coverings.
  • Advantageously, according to the invention, microchannels 10 are completely buried in the substrate 2 and the final integrated structure 1 is completely monocrystalline.
  • The steps of the process according to the invention for forming buried microchannels 10 in a completely monocrystalline integrated structure 1 are now described. As it will be seen in the following description, advantageously, according to the invention, these miniaturized channels are completely obtained through surface micromachining processes.
  • The process for forming buried microchannels 10 in an integrated structure 1 according to the invention comprises the steps of:
      • providing a monocrystalline silicon substrate 2;
      • forming on the substrate 2 surface a silicon nitride mask (Hard mask) through a CVD deposition technique; and
      • opening of a window having a convenient width L through photolithographic systems and following plasma etching.
  • In particular, as it is schematically shown in FIG. 2, above the substrate 2 a window is opened having a width L of about 1 mm and a depth H of about 9 mm along the substrate 2 direction, indicated in figure with the arrow F.
  • Advantageously according to the invention, the process provides a following plasma etching which uses the hard mask to form deep trenches 4 in the substrate 2, as shown in FIG. 2. Trenches 4 have side walls 4A and 4B which are substantially orthogonal to the substrate 2 surface.
  • The resulting structure then undergoes a further anisotropic wet etching, for example with a TMAH or KOH solution.
  • It is worth noting that solutions with different KOH or TMAH concentrations etch the monocrystalline silicon of the substrate 2 with speeds which highly depend on the crystallographic orientations and the dopant concentration of the substrate 2 itself. It is thus possible, by using a TMAH- or KOH-solution-etching, to form highly controllable and reproducible three-dimensional microchannels 10.
  • Advantageously according to the invention, trenches 4 are the precursors of microchannels 10.
  • The integrated structure 1, after the anisotropic etching step, has the shape shown in FIGS. 3A and 3B, wherein a single microchannel or a plurality of microchannels are shown, respectively.
  • Advantageously according to the invention, the resulting microchannels 10 have a rhombohedral shape.
  • In particular, the original shape of trenches 4 (shown in FIG. 2) turns into a pair of so-called rotated v-grooves V1 and V2, orthogonal to the surface S of the substrate 2 and defining rombohedron-shaped microchannels 10, as shown in FIG. 3A.
  • In other words, a bottleneck-shaped deep cavity is obtained, which has a small port on the surface S of the substrate 2.
  • In practice, while the etching time passes, because of the presence of a so-called under cut under the hard mask on the substrate 2 surface, microchannels 10 open upwardly changing the symmetry between the upper and lower part of their cavity, as schematically shown in FIG. 4.
  • It is, however, possible, by limiting the etching time, to obtain conveniently-sized microchannels by enlarging the depth of original trenches 4. In the alternative, it is possible to exploit the so-called etch stop effect by using as hard mask a heavily doped monocrystalline layer, as schematically shown in FIG. 5, wherein the substrate 2 and microchannels 10 are covered by a heavily doped hard mask layer capable of reducing under cut effects even when the substrate 2 etching time passes.
  • In a preferred embodiment, the layer 5 has a dopant concentration (for example, boron) higher than 1019 atoms/cm3.
  • It is also possible to use a predeposition on trench 4 walls of a layer of material 6 having a low etching speed (as, for example, the nitride).
  • In particular, this alternative embodiment of the process according to the invention provides a deposition of a nitride layer 6 followed by a plasma etching effective to open a region 7 at the trench 4 base, as shown in FIGS. 6A to 6F.
  • The process for realizing buried microchannels 10 in an integrated structure 1 according to this alternative embodiment of the invention comprises the steps of:
      • providing a monocrystalline silicon substrate 2;
      • growing a monocrystalline silicon layer 3 above the substrate 2; and
      • forming a mask by means of a photoelectric film 8 above the monocrystalline silicon layer 3, as schematically shown in FIG. 6A.
  • The process provides thus the steps of:
      • opening a plurality of windows through photolithographic systems and following plasma etching (FIG. 6B); and
      • forming a plurality of trenches 4 in correspondence with the plurality of windows (FIG. 6C).
  • Advantageously this alternative embodiment of the process according to the invention, provides therefore a deposition step of a nitride layer 6 (FIG. 6D), a removing step of the layer 6, an etching step of the silicon substrate in a lower part 9 of trenches 4 (FIG. 6E) and a plasma etching step effective to open a plurality of regions 7 at the trench 4 base (FIG. 6F).
  • In particular, the plasma etching step to open regions 7 at the trench 4 base is activated only in the area wherein the nitride layer 6 has been removed. It is essentially a so-called SCREAM process, wherein trench 4 walls are protected to localize the etching only under the trench base.
  • Even using this alternative embodiment of the process according to the invention, deep regions 7 are thus obtained, which have however a small surface opening in correspondence with the opening areas of trenches 4.
  • Advantageously according to the invention, trenches 4 are used for an anisotropic etching effective to obtain rhombohedral microchannels. The shape obtained is due to the different etching speeds of the different crystallographic directions.
  • The side walls 4A and 4B of trenches 4 undergo the etching anisotropic action and the erosion continues with different etching speeds due to the different atom coordination (in terms of bond quantity of silicon atoms directed towards the substrate).
  • In particular, atoms on planes of the (100) type have coordination two (i.e., two bonds directed towards the substrate), whereas atoms on planes of the (111) type have coordination three (i.e., three bonds directed towards the bulk); that is that they are more bonded.
  • Trenches 4 are directed along the directions (110) on the wafer surface of the (100) type. Planes (111) find on the wafer surface just the direction (110) and they are rotated with respect to the normal to the surface by about 54.7°.
  • In particular two planes are present, which pass in the upper part of trenches 4 and two planes passing in the lower part. All atoms along these directions have coordination three.
  • Advantageously according to the invention, the process starts by eroding the atoms having the lowest coordination which are characterized by a higher speed. After reaching the directions of planes (111) passing through/from the upper part and through/from the lower part of trenches 4, speed decreases by about a hundred times since it finds only atoms with coordination three, therefore it continues with the etching speed of planes (111) as shown in FIGS. 3A and 3B. In particular, a microchannel 10 opened towards the substrate 2 surface is obtained.
  • Advantageously, according to the invention, deep silicon cavities are thus obtained, being characterized by a small surface port whereto it is possible to apply a silicon deposition step to obtain a monocrystalline structure.
  • In other words, microchannels 10 have a bottle-section-shaped or rhomohedral precursor (obtained as above described) which is easily closed epitaxially in one embodiment or closed by deposition of a layer such as an oxide, polysilicon, nitride or other convenient material.
  • Advantageously according to the invention, the process provides a further epitaxial new growth step corresponding to the material used to close the upper part of the microchannel 10, as shown in FIG. 7A. It is thus possible to obtain completely buried monocrystalline silicon microchannels 10.
  • FIG. 7B shows for completeness the channel profile before (10A) and after (10B) the epitaxial new growth step. It happens thus that the monocrystalline material deposition occurs consistently also inside the microchannel 10.
  • It is also possible to close the upper part of microchannels by using other deposition techniques such as oxide or polysilicon or nitride deposition.
  • In conclusion, the process for realizing microchannels 10 buried in an integrated structure 1 according to the invention allows, thanks to the resulting etching form, the structure of the microchannel under the substrate 2 surface to be enlarged, but to keep, at the same time, the etching port small by means of trenches 4. The surface microchannel closing is thus performed by growing epitaxially the material.
  • Advantageously, according an embodiment of the invention, the integrated structure 1 is completely epitaxial even above microchannels 10 and it is performed by exploiting a deep cavity characterized by a small surface opening, which can be obtained in several kinds of processes, as well as an easy epitaxial new growth of this cavity.
  • Although preferred embodiments of the method and apparatus of the present invention have been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the spirit of the invention as set forth and defined by the following claims.

Claims (17)

  1. 1. An integrated structure, comprising:
    a monocrystalline silicon substrate within which at least one microchannel is formed which is nearly entirely buried inside said substrate.
  2. 2. The integrated structure according to claim 1, wherein the microchannel has a generally rhombohedral cross-sectional shape.
  3. 3. The integrated structure according to claim 1, further comprising an epitaxially grown silicon layer above the silicon substrate to completely enclose the microchannel in monocrystalline silicon.
  4. 4. The integrated structure according to claim 1, further comprising a layer above the silicon substrate to close completely enclose the microchannel.
  5. 5. The integrated structure according to claim 4, wherein the layer is an oxide, polysilicon or nitride deposition effective to close an upper part of said microchannel and completely bury the microchannel.
  6. 6. A fluid microchannel buried in an integrated structure comprising a monocrystalline silicon substrate, comprising:
    an anisotropically formed trench cavity in said substrate; and
    a completely monocrystalline structure which closes a top of the anisotropically formed trench cavity to define the fluid microchannel.
  7. 7. The fluid microchannel of claim 6 wherein the trench cavity has a generally rhombohedral cross-sectional shape.
  8. 8. The fluid microchannel of claim 6 wherein the completely monocrystalline structure which closes a top of the anisotropically formed trench cavity is epitaxially grown monocrystalline silicon.
  9. 9. An integrated structure fluid microchannel, comprising:
    an elongated trench formed in a monocrystalline silicon substrate and anisotropically etched to obtain a deep cavity having a narrow elongated surface port along a top surface of the substrate; and
    a closure of at least a portion of the narrow elongated surface port of the elongated trench to define with the deep cavity in the silicon substrate a tunnel-like microchannel.
  10. 10. The fluid microchannel of claim 9, wherein the closure comprises epitaxial new growth of the monocrystalline silicon substrate which closes the narrow elongated surface port and buries the deep cavity in monocrystalline silicon.
  11. 11. The fluid microchannel of claim 9, wherein the closure comprises an oxide, polysilicon or nitride deposition effective to close the narrow elongated surface port and bury the deep cavity.
  12. 12. An integrated structure microchannel, comprising:
    a narrow elongated trench formed in a monocrystalline silicon substrate and anisotropically wet etched to form a microchannel cavity structure having a generally rhombohedral cross-sectional shape with a top port substrate surface opening; and
    a closure of the top port substrate surface opening of the microchannel structure to enclose the microchannel cavity structure.
  13. 13. The microchannel of claim 12 wherein the closure comprises epitaxially grown monocrystalline silicon on a surface of the substrate to enclose the microchannel structure in monocrystalline silicon.
  14. 14. The microchannel of claim 12 further comprising a mask above the monocrystalline silicon substrate with an opening therein at the location of the trench.
  15. 15. The microchannel of claim 14 wherein the mask is a heavily doped monocrystalline layer deposition.
  16. 16. The microchannel of claim 12 wherein the narrow elongated trench has a width at a surface of the monocrystalline silicon substrate of about 1 micrometer.
  17. 17. The microchannel of claim 12 wherein the closure comprises a deposited layer of material taken from the group consisting of a polysilicon, a nitride or an oxide.
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US20080187463A1 (en) * 2007-02-07 2008-08-07 Wells David H Electromagnetic radiation interaction components, fluorimetry systems, semiconductor constructions, and electromagnetic radiation emitter and conduit construction

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US20040217447A1 (en) 2004-11-04 application
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US7063798B2 (en) 2006-06-20 grant

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