DE60216485D1 - Strukturen und verfahren zum selektiven anlegen einer muldenvorspannung an teile einer programmierbaren einrichtung - Google Patents

Strukturen und verfahren zum selektiven anlegen einer muldenvorspannung an teile einer programmierbaren einrichtung

Info

Publication number
DE60216485D1
DE60216485D1 DE60216485T DE60216485T DE60216485D1 DE 60216485 D1 DE60216485 D1 DE 60216485D1 DE 60216485 T DE60216485 T DE 60216485T DE 60216485 T DE60216485 T DE 60216485T DE 60216485 D1 DE60216485 D1 DE 60216485D1
Authority
DE
Germany
Prior art keywords
structures
parts
selectively applying
programmable equipment
terminal torque
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60216485T
Other languages
English (en)
Other versions
DE60216485T2 (de
Inventor
J Hart
P Young
Daniel Gitlin
Hua Shen
M Trimberger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Publication of DE60216485D1 publication Critical patent/DE60216485D1/de
Application granted granted Critical
Publication of DE60216485T2 publication Critical patent/DE60216485T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17792—Structural details for adapting physical parameters for operating speed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
DE60216485T 2001-09-18 2002-09-06 Strukturen und verfahren zum selektiven anlegen einer muldenvorspannung an teile einer programmierbaren einrichtung Expired - Lifetime DE60216485T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US956203 2001-09-18
US09/956,203 US6621325B2 (en) 2001-09-18 2001-09-18 Structures and methods for selectively applying a well bias to portions of a programmable device
PCT/US2002/028531 WO2003025804A2 (en) 2001-09-18 2002-09-06 Structures and methods for selectively applying a well bias to portions of a programmable device

Publications (2)

Publication Number Publication Date
DE60216485D1 true DE60216485D1 (de) 2007-01-11
DE60216485T2 DE60216485T2 (de) 2007-09-20

Family

ID=25497901

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60216485T Expired - Lifetime DE60216485T2 (de) 2001-09-18 2002-09-06 Strukturen und verfahren zum selektiven anlegen einer muldenvorspannung an teile einer programmierbaren einrichtung

Country Status (6)

Country Link
US (3) US6621325B2 (de)
EP (1) EP1428155B1 (de)
JP (1) JP2005503668A (de)
CA (1) CA2459416C (de)
DE (1) DE60216485T2 (de)
WO (1) WO2003025804A2 (de)

Families Citing this family (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6661253B1 (en) 2000-08-16 2003-12-09 Altera Corporation Passgate structures for use in low-voltage applications
US6781409B2 (en) * 2001-10-10 2004-08-24 Altera Corporation Apparatus and methods for silicon-on-insulator transistors in programmable logic devices
US7112978B1 (en) 2002-04-16 2006-09-26 Transmeta Corporation Frequency specific closed loop feedback control of integrated circuits
US7299427B2 (en) * 2002-08-30 2007-11-20 Lsi Corporation Radio prototyping system
US7295457B2 (en) * 2002-11-29 2007-11-13 International Business Machines Corporation Integrated circuit chip with improved array stability
US7334198B2 (en) * 2002-12-31 2008-02-19 Transmeta Corporation Software controlled transistor body bias
US6936898B2 (en) 2002-12-31 2005-08-30 Transmeta Corporation Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions
US7323367B1 (en) * 2002-12-31 2008-01-29 Transmeta Corporation Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions
US7949864B1 (en) 2002-12-31 2011-05-24 Vjekoslav Svilan Balanced adaptive body bias control
US7205758B1 (en) * 2004-02-02 2007-04-17 Transmeta Corporation Systems and methods for adjusting threshold voltage
DE60320314T2 (de) * 2003-02-20 2009-06-25 International Business Machines Corp. Testverfahren für integrierte schaltungen mit verwendung modifikation von well-spannungen
US6930510B2 (en) * 2003-03-03 2005-08-16 Xilinx, Inc. FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same
JP2005109179A (ja) * 2003-09-30 2005-04-21 National Institute Of Advanced Industrial & Technology 高速低消費電力論理装置
US7174528B1 (en) * 2003-10-10 2007-02-06 Transmeta Corporation Method and apparatus for optimizing body bias connections in CMOS circuits using a deep n-well grid structure
US7243312B1 (en) 2003-10-24 2007-07-10 Xilinx, Inc. Method and apparatus for power optimization during an integrated circuit design process
JP4221274B2 (ja) * 2003-10-31 2009-02-12 株式会社東芝 半導体集積回路および電源電圧・基板バイアス制御回路
US7649402B1 (en) 2003-12-23 2010-01-19 Tien-Min Chen Feedback-controlled body-bias voltage source
US7107566B1 (en) * 2004-01-22 2006-09-12 Altera Corporation Programmable logic device design tools with gate leakage reduction capabilities
US7816742B1 (en) 2004-09-30 2010-10-19 Koniaris Kleanthes G Systems and methods for integrated circuits comprising multiple body biasing domains
US7859062B1 (en) 2004-02-02 2010-12-28 Koniaris Kleanthes G Systems and methods for integrated circuits comprising multiple body biasing domains
US7645673B1 (en) * 2004-02-03 2010-01-12 Michael Pelham Method for generating a deep N-well pattern for an integrated circuit design
US7287171B1 (en) 2004-03-08 2007-10-23 Altera Corporation Systems and methods for reducing static and total power consumption in programmable logic device architectures
US7188266B1 (en) * 2004-03-08 2007-03-06 Altera Corporation Systems and methods for reducing static and total power consumption in a programmable logic device
US7388260B1 (en) 2004-03-31 2008-06-17 Transmeta Corporation Structure for spanning gap in body-bias voltage routing structure
US7129745B2 (en) * 2004-05-19 2006-10-31 Altera Corporation Apparatus and methods for adjusting performance of integrated circuits
US7348827B2 (en) * 2004-05-19 2008-03-25 Altera Corporation Apparatus and methods for adjusting performance of programmable logic devices
US7400167B2 (en) * 2005-08-16 2008-07-15 Altera Corporation Apparatus and methods for optimizing the performance of programmable logic devices
US7292065B2 (en) * 2004-08-03 2007-11-06 Altera Corporation Enhanced passgate structures for reducing leakage current
CN1755835B (zh) * 2004-09-27 2011-11-23 国际商业机器公司 具有改进的阵列稳定性的集成电路芯片
US7509504B1 (en) 2004-09-30 2009-03-24 Transmeta Corporation Systems and methods for control of integrated circuits comprising body biasing systems
US7122867B2 (en) * 2004-11-19 2006-10-17 United Microelectronics Corp. Triple well structure and method for manufacturing the same
US7151697B2 (en) * 2004-11-30 2006-12-19 Infineon Technologies Ag Non-volatile semiconductor memory
US20060119382A1 (en) * 2004-12-07 2006-06-08 Shumarayev Sergey Y Apparatus and methods for adjusting performance characteristics of programmable logic devices
US7274247B2 (en) * 2005-04-04 2007-09-25 Freescale Semiconductor, Inc. System, method and program product for well-bias set point adjustment
US7486098B2 (en) * 2005-06-16 2009-02-03 International Business Machines Corporation Integrated circuit testing method using well bias modification
US7305647B1 (en) 2005-07-28 2007-12-04 Transmeta Corporation Using standard pattern tiles and custom pattern tiles to generate a semiconductor design layout having a deep well structure for routing body-bias voltage
US7295036B1 (en) * 2005-11-30 2007-11-13 Altera Corporation Method and system for reducing static leakage current in programmable logic devices
US7183800B1 (en) * 2005-12-14 2007-02-27 Altera Corporation Apparatus and methods for programmable logic devices with improved performance characteristics
US7580824B1 (en) * 2005-12-21 2009-08-25 Altera Corporation Apparatus and methods for modeling power characteristics of electronic circuitry
KR100728571B1 (ko) * 2006-02-09 2007-06-15 주식회사 하이닉스반도체 반도체 메모리의 데이터 센싱장치
US7936184B2 (en) * 2006-02-24 2011-05-03 Altera Corporation Apparatus and methods for adjusting performance of programmable logic devices
US7490303B2 (en) * 2006-03-03 2009-02-10 International Business Machines Corporation Identifying parasitic diode(s) in an integrated circuit physical design
US7330049B2 (en) * 2006-03-06 2008-02-12 Altera Corporation Adjustable transistor body bias generation circuitry with latch-up prevention
US7355437B2 (en) 2006-03-06 2008-04-08 Altera Corporation Latch-up prevention circuitry for integrated circuits with transistor body biasing
US7495471B2 (en) 2006-03-06 2009-02-24 Altera Corporation Adjustable transistor body bias circuitry
US7389485B1 (en) 2006-03-28 2008-06-17 Xilinx, Inc. Methods of routing low-power designs in programmable logic devices having heterogeneous routing architectures
US7463057B1 (en) 2006-03-29 2008-12-09 Altera Corporation Integrated circuits with adjustable memory element power supplies
JP4799255B2 (ja) * 2006-04-17 2011-10-26 パナソニック株式会社 半導体集積回路
JP2007311535A (ja) * 2006-05-18 2007-11-29 Matsushita Electric Ind Co Ltd セル配置方法
US7466190B2 (en) * 2006-07-24 2008-12-16 Lattice Semiconductor Corporation Charge pump with four-well transistors
US20080180129A1 (en) * 2006-08-31 2008-07-31 Actel Corporation Fpga architecture with threshold voltage compensation and reduced leakage
JP2008263261A (ja) * 2007-04-10 2008-10-30 National Institute Of Advanced Industrial & Technology 再構成可能集積回路
US7675317B2 (en) * 2007-09-14 2010-03-09 Altera Corporation Integrated circuits with adjustable body bias and power supply circuitry
US7742325B2 (en) * 2007-12-17 2010-06-22 Suvolta, Inc. Swapped-body RAM architecture
JP5194805B2 (ja) 2008-01-08 2013-05-08 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US8102187B2 (en) * 2008-05-02 2012-01-24 Texas Instruments Incorporated Localized calibration of programmable digital logic cells
US7952423B2 (en) * 2008-09-30 2011-05-31 Altera Corporation Process/design methodology to enable high performance logic and analog circuits using a single process
US8987868B1 (en) 2009-02-24 2015-03-24 Xilinx, Inc. Method and apparatus for programmable heterogeneous integration of stacked semiconductor die
US8072237B1 (en) 2009-06-04 2011-12-06 Altera Corporation Computer-aided design tools and memory element power supply circuitry for selectively overdriving circuit blocks
US7893712B1 (en) 2009-09-10 2011-02-22 Xilinx, Inc. Integrated circuit with a selectable interconnect circuit for low power or high performance operation
US9570974B2 (en) 2010-02-12 2017-02-14 Infineon Technologies Ag High-frequency switching circuit
EP2369622B1 (de) * 2010-03-24 2015-10-14 STMicroelectronics Rousset SAS Verfahren und Vorrichtung für Gegenmassnahme gegenüber einem Angriff durch Fehlerinjektion in einem elektronischen Mikroschaltungskarte
US9015023B2 (en) 2010-05-05 2015-04-21 Xilinx, Inc. Device specific configuration of operating voltage
US8633731B1 (en) 2011-08-09 2014-01-21 Altera Corporation Programmable integrated circuit with thin-oxide passgates
US9287253B2 (en) 2011-11-04 2016-03-15 Synopsys, Inc. Method and apparatus for floating or applying voltage to a well of an integrated circuit
US9436250B1 (en) 2011-12-19 2016-09-06 Altera Corporation Apparatus for improving power consumption of communication circuitry and associated methods
US8896344B1 (en) 2013-01-04 2014-11-25 Altera Corporation Heterogeneous programmable device and configuration software adapted therefor
US9000490B2 (en) 2013-04-19 2015-04-07 Xilinx, Inc. Semiconductor package having IC dice and voltage tuners
WO2015045135A1 (ja) * 2013-09-30 2015-04-02 株式会社日立製作所 プログラマブルロジックデバイス、及び、論理集積ツール
US9444460B1 (en) 2013-11-22 2016-09-13 Altera Corporation Integrated circuits with programmable overdrive capabilities
US9484919B1 (en) 2014-04-30 2016-11-01 Xilinx, Inc. Selection of logic paths for redundancy
US9275180B1 (en) 2014-07-14 2016-03-01 Xilinx, Inc. Programmable integrated circuit having different types of configuration memory
KR102101836B1 (ko) 2014-07-24 2020-04-17 삼성전자 주식회사 딜레이 셀 및 이를 적용하는 지연 동기 루프 회로와 위상 동기 루프 회로
US9628081B2 (en) 2014-08-12 2017-04-18 Xilinx, Inc. Interconnect circuits having low threshold voltage P-channel transistors for a programmable integrated circuit
US9378326B2 (en) * 2014-09-09 2016-06-28 International Business Machines Corporation Critical region identification
US9621033B2 (en) * 2015-09-09 2017-04-11 Nxp Usa, Inc. Charge pump circuit for providing multiplied voltage
US10121534B1 (en) 2015-12-18 2018-11-06 Altera Corporation Integrated circuit with overdriven and underdriven pass gates
US10378967B1 (en) 2016-10-27 2019-08-13 Rambus Inc. Dual temperature band integrated circuit device
WO2023110423A1 (en) 2021-12-17 2023-06-22 RACYICS GmbH An adaptive body biasing system for silicon on insulator semiconductor devices and a production test method for testing single or multiple adaptive body bias generators

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US544198A (en) * 1895-08-06 Half to irvin w
JP3253389B2 (ja) * 1992-03-31 2002-02-04 株式会社東芝 半導体集積回路装置
US5461338A (en) * 1992-04-17 1995-10-24 Nec Corporation Semiconductor integrated circuit incorporated with substrate bias control circuit
KR0169157B1 (ko) * 1993-11-29 1999-02-01 기다오까 다까시 반도체 회로 및 mos-dram
US5487033A (en) * 1994-06-28 1996-01-23 Intel Corporation Structure and method for low current programming of flash EEPROMS
US5661685A (en) 1995-09-25 1997-08-26 Xilinx, Inc. Programmable logic device with configurable power supply
US6175952B1 (en) * 1997-05-27 2001-01-16 Altera Corporation Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions
JPH1070243A (ja) * 1996-05-30 1998-03-10 Toshiba Corp 半導体集積回路装置およびその検査方法およびその検査装置
JPH1079193A (ja) * 1996-07-11 1998-03-24 Toshiba Microelectron Corp 半導体装置
US5880620A (en) 1997-04-22 1999-03-09 Xilinx, Inc. Pass gate circuit with body bias control
US5929695A (en) * 1997-06-02 1999-07-27 Stmicroelectronics, Inc. Integrated circuit having selective bias of transistors for low voltage and low standby current and related methods
JP3814385B2 (ja) * 1997-10-14 2006-08-30 株式会社ルネサステクノロジ 半導体集積回路装置
JP3777768B2 (ja) * 1997-12-26 2006-05-24 株式会社日立製作所 半導体集積回路装置およびセルライブラリを記憶した記憶媒体および半導体集積回路の設計方法
US6590419B1 (en) * 1999-10-12 2003-07-08 Altera Toronto Co. Heterogeneous interconnection architecture for programmable logic devices
US6369630B1 (en) * 1999-11-24 2002-04-09 Bae Systems Information And Electronic Systems Integration Inc. Single-event upset hardened reconfigurable bi-stable CMOS latch
JP2001203325A (ja) * 2000-01-19 2001-07-27 Hitachi Ltd 半導体集積回路装置とデジタル集積回路の設計方法
US6630838B1 (en) * 2001-01-23 2003-10-07 Xilinx, Inc. Method for implementing dynamic burn-in testing using static test signals

Also Published As

Publication number Publication date
CA2459416C (en) 2010-04-06
WO2003025804A3 (en) 2004-02-05
US6777978B2 (en) 2004-08-17
US20040025135A1 (en) 2004-02-05
US20040216074A1 (en) 2004-10-28
EP1428155A2 (de) 2004-06-16
US6621325B2 (en) 2003-09-16
CA2459416A1 (en) 2003-03-27
US7089527B2 (en) 2006-08-08
EP1428155B1 (de) 2006-11-29
US20030053335A1 (en) 2003-03-20
DE60216485T2 (de) 2007-09-20
JP2005503668A (ja) 2005-02-03
WO2003025804A2 (en) 2003-03-27

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