DE60212012D1 - Taktschaltung fähig zur Unterdrückung der Phasenverschiebung während einer Umschaltung von Aktiventakt bis Bereitschaftstakt - Google Patents

Taktschaltung fähig zur Unterdrückung der Phasenverschiebung während einer Umschaltung von Aktiventakt bis Bereitschaftstakt

Info

Publication number
DE60212012D1
DE60212012D1 DE60212012T DE60212012T DE60212012D1 DE 60212012 D1 DE60212012 D1 DE 60212012D1 DE 60212012 T DE60212012 T DE 60212012T DE 60212012 T DE60212012 T DE 60212012T DE 60212012 D1 DE60212012 D1 DE 60212012D1
Authority
DE
Germany
Prior art keywords
clock
changeover
suppressing
phase shift
circuit capable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60212012T
Other languages
English (en)
Other versions
DE60212012T2 (de
Inventor
Yasuaki Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE60212012D1 publication Critical patent/DE60212012D1/de
Publication of DE60212012T2 publication Critical patent/DE60212012T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
DE60212012T 2001-08-07 2002-08-06 Taktschaltung, die während einer Umschaltung von Aktivtakt auf Bereitschafstakt die Phasenverschiebung unterdrücken kann Expired - Fee Related DE60212012T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001239279 2001-08-07
JP2001239279A JP3531630B2 (ja) 2001-08-07 2001-08-07 クロック生成回路

Publications (2)

Publication Number Publication Date
DE60212012D1 true DE60212012D1 (de) 2006-07-20
DE60212012T2 DE60212012T2 (de) 2007-01-04

Family

ID=19070054

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60212012T Expired - Fee Related DE60212012T2 (de) 2001-08-07 2002-08-06 Taktschaltung, die während einer Umschaltung von Aktivtakt auf Bereitschafstakt die Phasenverschiebung unterdrücken kann

Country Status (4)

Country Link
US (1) US6653874B2 (de)
EP (1) EP1283597B1 (de)
JP (1) JP3531630B2 (de)
DE (1) DE60212012T2 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003061129A1 (fr) * 2002-01-16 2003-07-24 Mitsubishi Denki Kabushiki Kaisha Circuit generateur d'impulsions
AU2002321951A1 (en) * 2002-08-30 2004-03-19 Telefonaktiebolaget Lm Ericsson (Publ) Method and arrangement for reducing phase jumps when switching between synchronisation sources
WO2004040835A1 (ja) * 2002-11-01 2004-05-13 Fujitsu Limited データ処理回路
KR100533915B1 (ko) * 2003-10-21 2005-12-06 한국전자통신연구원 클럭 신호의 연속성을 보장하는 클럭 신호 선택 장치 및방법
US7747237B2 (en) * 2004-04-09 2010-06-29 Skyworks Solutions, Inc. High agility frequency synthesizer phase-locked loop
US7733919B2 (en) * 2004-07-12 2010-06-08 General Instrument Corporation Method and apparatus for processing transport stream packets to compensate for jitter
JP2006333382A (ja) * 2005-05-30 2006-12-07 Fujitsu Ltd システムクロック装置
JP2007129404A (ja) * 2005-11-02 2007-05-24 Olympus Corp カメラシステム
US7539278B2 (en) * 2005-12-02 2009-05-26 Altera Corporation Programmable transceivers that are able to operate over wide frequency ranges
EP1814230A1 (de) * 2006-01-30 2007-08-01 Infineon Technologies AG Phasenregelschleife mit digitalem Loop-Filter
JP4745127B2 (ja) * 2006-05-23 2011-08-10 ルネサスエレクトロニクス株式会社 クロック切替回路
DE102006024471A1 (de) * 2006-05-24 2007-12-06 Xignal Technologies Ag Umschaltbarer Phasenregelkreis sowie Verfahren zum Betrieb eines umschaltbaren Phasenregelkreises
TWI316793B (en) * 2006-06-28 2009-11-01 Realtek Semiconductor Corp Frequency synthesizer with a plurality of frequency locking circuits
US7355462B1 (en) * 2006-07-10 2008-04-08 Altera Corporation Phase lock loop and method for operating the same
TWI332318B (en) * 2006-09-07 2010-10-21 Realtek Semiconductor Corp Multiloop phase locked loop circuit
US7629828B1 (en) * 2007-04-27 2009-12-08 Zilog, Inc. Glitch-free clock multiplexer that provides an output clock signal based on edge detection
US7902886B2 (en) * 2007-10-30 2011-03-08 Diablo Technologies Inc. Multiple reference phase locked loop
WO2014146274A1 (en) * 2013-03-21 2014-09-25 Telefonaktiebolaget L M Ericsson (Publ) Method and apparatus for implementing clock holdover
US9698808B1 (en) * 2016-10-27 2017-07-04 Cavium, Inc. Phase measurement and correction circuitry
US9929722B1 (en) * 2017-01-30 2018-03-27 International Business Machines Corporation Wire capacitor for transmitting AC signals
JP7147260B2 (ja) * 2018-05-16 2022-10-05 セイコーエプソン株式会社 回路装置、発振器、電子機器及び移動体
KR20210082772A (ko) * 2019-12-26 2021-07-06 에스케이하이닉스 주식회사 디지털 필터 및 이를 포함하는 온도 센서

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5726607A (en) * 1992-06-15 1998-03-10 Adc Telecommunications, Inc. Phase locked loop using a counter and a microcontroller to produce VCXO control signals
JPH0964732A (ja) 1995-08-24 1997-03-07 Toshiba Corp 同期クロック生成回路
US5610558A (en) * 1995-11-03 1997-03-11 Motorola, Inc. Controlled tracking of oscillators in a circuit with multiple frequency sensitive elements
JPH09289447A (ja) * 1996-04-22 1997-11-04 Sony Corp Ｐｌｌ回路
JP2962255B2 (ja) 1996-12-25 1999-10-12 安藤電気株式会社 クロック系の冗長構成における位相制御方式
JP2944607B2 (ja) * 1998-02-12 1999-09-06 日本電気アイシーマイコンシステム株式会社 ディジタルｐｌｌ回路とクロックの生成方法
US6204732B1 (en) * 1999-02-09 2001-03-20 Eci Telecom Ltd Apparatus for clock signal distribution, with transparent switching capability between two clock distribution units
JP3062179B1 (ja) 1999-03-09 2000-07-10 エヌイーシーテレネットワークス株式会社 冗長系クロック位相調整回路

Also Published As

Publication number Publication date
EP1283597A2 (de) 2003-02-12
US20030030475A1 (en) 2003-02-13
JP3531630B2 (ja) 2004-05-31
JP2003051742A (ja) 2003-02-21
DE60212012T2 (de) 2007-01-04
US6653874B2 (en) 2003-11-25
EP1283597A3 (de) 2003-05-21
EP1283597B1 (de) 2006-06-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee