DE60207144D1 - Schaltungsanordnung einer Rückwandleiterplatte - Google Patents

Schaltungsanordnung einer Rückwandleiterplatte

Info

Publication number
DE60207144D1
DE60207144D1 DE60207144T DE60207144T DE60207144D1 DE 60207144 D1 DE60207144 D1 DE 60207144D1 DE 60207144 T DE60207144 T DE 60207144T DE 60207144 T DE60207144 T DE 60207144T DE 60207144 D1 DE60207144 D1 DE 60207144D1
Authority
DE
Germany
Prior art keywords
circuit arrangement
backplane board
backplane
board
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60207144T
Other languages
English (en)
Other versions
DE60207144T2 (de
Inventor
James J Deblanc
Carl R Haynie
James L White
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE60207144D1 publication Critical patent/DE60207144D1/de
Publication of DE60207144T2 publication Critical patent/DE60207144T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/409—Mechanical coupling
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/14—Mounting supporting structure in casing or on frame or rack
    • H05K7/1462—Mounting supporting structure in casing or on frame or rack for programmable logic controllers [PLC] for automation or industrial process control
    • H05K7/1475—Bus assemblies for establishing communication between PLC modules
    • H05K7/1477—Bus assemblies for establishing communication between PLC modules including backplanes

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Debugging And Monitoring (AREA)
  • Details Of Connecting Devices For Male And Female Coupling (AREA)
  • Dc Digital Transmission (AREA)
DE60207144T 2001-06-01 2002-05-30 Schaltungsanordnung einer Rückwandleiterplatte Expired - Fee Related DE60207144T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US872924 2001-06-01
US09/872,924 US6910089B2 (en) 2001-06-01 2001-06-01 Fault tolerant bus for highly available storage enclosure

Publications (2)

Publication Number Publication Date
DE60207144D1 true DE60207144D1 (de) 2005-12-15
DE60207144T2 DE60207144T2 (de) 2006-08-10

Family

ID=25360609

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60207144T Expired - Fee Related DE60207144T2 (de) 2001-06-01 2002-05-30 Schaltungsanordnung einer Rückwandleiterplatte

Country Status (6)

Country Link
US (1) US6910089B2 (de)
EP (1) EP1262877B1 (de)
JP (1) JP2003036128A (de)
KR (1) KR20020092232A (de)
DE (1) DE60207144T2 (de)
TW (1) TW589564B (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7281063B2 (en) * 2003-07-22 2007-10-09 Hewlett-Packard Development Company, L.P. Signal routing circuit board coupling controller and storage array circuit board for storage system
US20050289284A1 (en) * 2004-06-24 2005-12-29 Ge Chang High speed memory modules
US7461101B2 (en) 2004-07-13 2008-12-02 International Business Machines Corporation Method for reducing data loss and unavailability by integrating multiple levels of a storage hierarchy
ES2635339T3 (es) 2008-05-21 2017-10-03 Hewlett-Packard Development Company, L.P. Bus serie de múltiples salidas con detección de ubicación y procedimiento
US20100262753A1 (en) * 2009-04-08 2010-10-14 Fujitsu Limited Method and apparatus for connecting multiple memory devices to a controller
US9454504B2 (en) 2010-09-30 2016-09-27 Hewlett-Packard Development Company, L.P. Slave device bit sequence zero driver
US9548808B2 (en) 2014-11-11 2017-01-17 International Business Machines Corporation Dynamic optical channel sparing in an industry standard input/output subsystem

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4445048A (en) * 1980-04-04 1984-04-24 Rolm Corporation High speed ribbon cable bus
JP2845480B2 (ja) * 1989-03-14 1999-01-13 株式会社東芝 信号分配方式
US5224021A (en) * 1989-10-20 1993-06-29 Matsushita Electric Industrial Co., Ltd. Surface-mount network device
US5019728A (en) * 1990-09-10 1991-05-28 Ncr Corporation High speed CMOS backpanel transceiver
US5382841A (en) * 1991-12-23 1995-01-17 Motorola, Inc. Switchable active bus termination circuit
JP2882266B2 (ja) * 1993-12-28 1999-04-12 株式会社日立製作所 信号伝送装置及び回路ブロック
US5767695A (en) * 1993-12-28 1998-06-16 Takekuma; Toshitsugu Fast transmission line implemented with receiver, driver, terminator and IC arrangements
GB9405855D0 (en) * 1994-03-24 1994-05-11 Int Computers Ltd Computer system
US5564024A (en) * 1994-08-02 1996-10-08 Pemberton; Adam C. Apparatus for connecting and disconnecting peripheral devices to a powered bus
US5612634A (en) * 1994-09-26 1997-03-18 Zilog, Inc. Circuit for sensing whether or not an add-in board is inserted into a bus connector of a mother board
US5620331A (en) * 1994-12-15 1997-04-15 Methode Electronics, Inc. Feed-thru IDC terminator
US5578940A (en) * 1995-04-04 1996-11-26 Rambus, Inc. Modular bus with single or double parallel termination
US5568060A (en) * 1995-07-20 1996-10-22 Transwitch Corporation Circuit board insertion circuitry for high reliability backplanes
US5721497A (en) * 1996-01-23 1998-02-24 Sun Microsystems, Inc. Cold termination for a bus
US5955703A (en) * 1996-02-28 1999-09-21 Methode Electronics, Inc. Circuitized electrical cable and method of assembling same
US5945886A (en) * 1996-09-20 1999-08-31 Sldram, Inc. High-speed bus structure for printed circuit boards
US6265912B1 (en) * 1997-08-06 2001-07-24 Nec Corporation High-speed bus capable of effectively suppressing a noise on a bus line
US6011710A (en) * 1997-10-30 2000-01-04 Hewlett-Packard Company Capacitance reducing memory system, device and method
JP3964528B2 (ja) * 1998-03-02 2007-08-22 富士通株式会社 シリアルバス高速化回路
JP2000122761A (ja) * 1998-10-14 2000-04-28 Hitachi Ltd バスシステム及びそれを用いたメモリシステム
US6198307B1 (en) * 1998-10-26 2001-03-06 Rambus Inc. Output driver circuit with well-controlled output impedance
US6222389B1 (en) * 1999-03-25 2001-04-24 International Business Machines Corporation Assisted gunning transceiver logic (AGTL) bus driver
US6434647B1 (en) * 1999-05-27 2002-08-13 Microsoft Corporation Reflected-wave bus termination
US6603323B1 (en) * 2000-07-10 2003-08-05 Formfactor, Inc. Closed-grid bus architecture for wafer interconnect structure
US6369605B1 (en) * 2000-09-18 2002-04-09 Intel Corporation Self-terminated driver to prevent signal reflections of transmissions between electronic devices

Also Published As

Publication number Publication date
US6910089B2 (en) 2005-06-21
KR20020092232A (ko) 2002-12-11
US20030028698A1 (en) 2003-02-06
DE60207144T2 (de) 2006-08-10
TW589564B (en) 2004-06-01
EP1262877B1 (de) 2005-11-09
EP1262877A2 (de) 2002-12-04
EP1262877A3 (de) 2003-10-15
JP2003036128A (ja) 2003-02-07

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee