DE602006005134D1 - Magnetische Tunnelübergangszelle für Logikschaltung und Betriebsverfahren dafür - Google Patents
Magnetische Tunnelübergangszelle für Logikschaltung und Betriebsverfahren dafürInfo
- Publication number
- DE602006005134D1 DE602006005134D1 DE602006005134T DE602006005134T DE602006005134D1 DE 602006005134 D1 DE602006005134 D1 DE 602006005134D1 DE 602006005134 T DE602006005134 T DE 602006005134T DE 602006005134 T DE602006005134 T DE 602006005134T DE 602006005134 D1 DE602006005134 D1 DE 602006005134D1
- Authority
- DE
- Germany
- Prior art keywords
- logic circuitry
- tunnel junction
- magnetic tunnel
- junction cell
- operation therefor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/18—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using galvano-magnetic devices, e.g. Hall-effect devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Hall/Mr Elements (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020060017060A KR100682967B1 (ko) | 2006-02-22 | 2006-02-22 | 자기터널접합 셀을 이용한 배타적 논리합 논리회로 및 상기논리회로의 구동 방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602006005134D1 true DE602006005134D1 (de) | 2009-03-26 |
Family
ID=38050068
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602006005134T Active DE602006005134D1 (de) | 2006-02-22 | 2006-08-11 | Magnetische Tunnelübergangszelle für Logikschaltung und Betriebsverfahren dafür |
Country Status (5)
Country | Link |
---|---|
US (1) | US7439770B2 (de) |
EP (1) | EP1826770B1 (de) |
JP (1) | JP5221043B2 (de) |
KR (1) | KR100682967B1 (de) |
DE (1) | DE602006005134D1 (de) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7397277B2 (en) * | 2005-10-17 | 2008-07-08 | Northern Lights Semiconductor Corp. | Magnetic transistor circuit with the EXOR function |
JP2009059884A (ja) * | 2007-08-31 | 2009-03-19 | Tokyo Institute Of Technology | 電子回路 |
KR100961723B1 (ko) | 2008-02-18 | 2010-06-10 | 이화여자대학교 산학협력단 | 스핀 토크 변환을 이용한 자기터널접합 소자를 사용한xor 논리 연산장치 |
JP4516137B2 (ja) * | 2008-03-27 | 2010-08-04 | 株式会社東芝 | 半導体集積回路 |
JP5603049B2 (ja) * | 2009-10-28 | 2014-10-08 | 国立大学法人東北大学 | 電子回路 |
KR20110057601A (ko) | 2009-11-24 | 2011-06-01 | 삼성전자주식회사 | 비휘발성 논리 회로, 상기 비휘발성 논리 회로를 포함하는 집적 회로 및 상기 집적 회로의 동작 방법 |
JP5874647B2 (ja) * | 2011-01-06 | 2016-03-02 | 日本電気株式会社 | 不揮発論理演算デバイス |
FR3031643B1 (fr) * | 2015-01-09 | 2018-03-02 | Easybroadcast | Procede de gestion et de fonctionnement protocolaire d'un reseau de distribution de contenu |
US10333523B2 (en) * | 2015-05-28 | 2019-06-25 | Intel Corporation | Exclusive-OR logic device with spin orbit torque effect |
US9503085B1 (en) * | 2015-09-30 | 2016-11-22 | The Research Foundation For The State University Of New York | Exclusive-OR gate using magneto-electric tunnel junctions |
US9692413B2 (en) | 2015-09-30 | 2017-06-27 | The Research Foundation For The State University Of New York | Configurable exclusive-OR / exclusive-NOR gate using magneto-electric tunnel junctions |
KR101843917B1 (ko) | 2016-09-06 | 2018-03-30 | 한국과학기술연구원 | 스핀-궤도 결합의 차이를 이용한 상보성 논리 소자 및 그 제조 방법 |
KR102582672B1 (ko) | 2016-11-01 | 2023-09-25 | 삼성전자주식회사 | 자기 터널 접합 소자를 포함하는 논리 회로 |
JP6545853B1 (ja) * | 2018-03-20 | 2019-07-17 | 株式会社東芝 | 磁気デバイス |
JP7311733B2 (ja) * | 2019-10-17 | 2023-07-20 | Yoda-S株式会社 | 磁気デバイス及び演算装置 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6034887A (en) * | 1998-08-05 | 2000-03-07 | International Business Machines Corporation | Non-volatile magnetic memory cell and devices |
US6391483B1 (en) * | 1999-03-30 | 2002-05-21 | Carnegie Mellon University | Magnetic device and method of forming same |
US6498747B1 (en) * | 2002-02-08 | 2002-12-24 | Infineon Technologies Ag | Magnetoresistive random access memory (MRAM) cross-point array with reduced parasitic effects |
US6783994B2 (en) * | 2002-04-26 | 2004-08-31 | Freescale Semiconductor, Inc. | Method of fabricating a self-aligned magnetic tunneling junction and via contact |
US6653704B1 (en) * | 2002-09-24 | 2003-11-25 | International Business Machines Corporation | Magnetic memory with tunnel junction memory cells and phase transition material for controlling current to the cells |
US7027319B2 (en) * | 2003-06-19 | 2006-04-11 | Hewlett-Packard Development Company, L.P. | Retrieving data stored in a magnetic integrated memory |
US6987692B2 (en) * | 2003-10-03 | 2006-01-17 | Hewlett-Packard Development Company, L.P. | Magnetic memory having angled third conductor |
US20050269612A1 (en) * | 2004-05-11 | 2005-12-08 | Integrated Magnetoelectronics | Solid-state component based on current-induced magnetization reversal |
-
2006
- 2006-02-22 KR KR1020060017060A patent/KR100682967B1/ko active IP Right Grant
- 2006-08-11 DE DE602006005134T patent/DE602006005134D1/de active Active
- 2006-08-11 EP EP06118793A patent/EP1826770B1/de active Active
-
2007
- 2007-01-17 US US11/654,002 patent/US7439770B2/en active Active
- 2007-01-30 JP JP2007019517A patent/JP5221043B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
EP1826770A1 (de) | 2007-08-29 |
KR100682967B1 (ko) | 2007-02-15 |
JP2007228574A (ja) | 2007-09-06 |
US7439770B2 (en) | 2008-10-21 |
EP1826770B1 (de) | 2009-02-11 |
JP5221043B2 (ja) | 2013-06-26 |
US20080013369A1 (en) | 2008-01-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |