DE602005014980D1 - Verfahren und vorrichtung für widerstand gegen har - Google Patents

Verfahren und vorrichtung für widerstand gegen har

Info

Publication number
DE602005014980D1
DE602005014980D1 DE602005014980T DE602005014980T DE602005014980D1 DE 602005014980 D1 DE602005014980 D1 DE 602005014980D1 DE 602005014980 T DE602005014980 T DE 602005014980T DE 602005014980 T DE602005014980 T DE 602005014980T DE 602005014980 D1 DE602005014980 D1 DE 602005014980D1
Authority
DE
Germany
Prior art keywords
access
internal registers
interface
lock
master
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005014980T
Other languages
English (en)
Inventor
Paul Stewart Yosim
Irfan Rashid
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE602005014980D1 publication Critical patent/DE602005014980D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2105—Dual mode as a secondary aspect

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Storage Device Security (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Networks Using Active Elements (AREA)
DE602005014980T 2004-04-29 2005-04-04 Verfahren und vorrichtung für widerstand gegen har Active DE602005014980D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/835,462 US7274283B2 (en) 2004-04-29 2004-04-29 Method and apparatus for resisting hardware hacking through internal register interface
PCT/EP2005/051499 WO2005106615A1 (en) 2004-04-29 2005-04-04 Method and apparatus for resisting hardware hacking through internal register interface

Publications (1)

Publication Number Publication Date
DE602005014980D1 true DE602005014980D1 (de) 2009-07-30

Family

ID=34962535

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005014980T Active DE602005014980D1 (de) 2004-04-29 2005-04-04 Verfahren und vorrichtung für widerstand gegen har

Country Status (9)

Country Link
US (1) US7274283B2 (de)
EP (1) EP1763715B1 (de)
JP (1) JP4771550B2 (de)
KR (1) KR100961807B1 (de)
CN (1) CN100458643C (de)
AT (1) ATE434228T1 (de)
DE (1) DE602005014980D1 (de)
TW (1) TWI344690B (de)
WO (1) WO2005106615A1 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
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FR2875949A1 (fr) * 2004-09-28 2006-03-31 St Microelectronics Sa Verrouillage d'un circuit integre
US7442583B2 (en) * 2004-12-17 2008-10-28 International Business Machines Corporation Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable
US20080061817A1 (en) * 2004-12-17 2008-03-13 International Business Machines Corporation Changing Chip Function Based on Fuse States
US9652637B2 (en) 2005-05-23 2017-05-16 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and system for allowing no code download in a code download scheme
US7398441B1 (en) * 2005-12-21 2008-07-08 Rockwell Collins, Inc. System and method for providing secure boundary scan interface access
US9904809B2 (en) 2006-02-27 2018-02-27 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and system for multi-level security initialization and configuration
JP2007265023A (ja) * 2006-03-28 2007-10-11 Fujitsu Ltd 情報処理装置及びその管理方法並びに管理プログラム
US20070290715A1 (en) * 2006-06-19 2007-12-20 David Baer Method And System For Using One-Time Programmable (OTP) Read-Only Memory (ROM) To Configure Chip Usage Features
US9489318B2 (en) 2006-06-19 2016-11-08 Broadcom Corporation Method and system for accessing protected memory
US8146163B2 (en) * 2006-11-09 2012-03-27 International Business Machines Corporation Method and system for securing personal computing devices from unauthorized data copying and removal
US20080142606A1 (en) * 2006-12-19 2008-06-19 Ping-Chang Wu E-fuse bar code structure and method of using the same
TW200832436A (en) * 2007-01-26 2008-08-01 Holtek Semiconductor Inc Data securing method and structure for non-volatile storage device
US8402241B2 (en) * 2007-10-02 2013-03-19 Advanced Micro Devices, Inc. Method and apparatus to control access to device enable features
US8230495B2 (en) * 2009-03-27 2012-07-24 International Business Machines Corporation Method for security in electronically fused encryption keys
FR2958063B1 (fr) * 2010-03-26 2012-04-20 Thales Sa Dispositif permettant de securiser un bus de type jtag
KR101725505B1 (ko) * 2010-12-07 2017-04-11 삼성전자주식회사 해킹 검출 장치, 집적 회로 및 해킹 검출 방법
DE102013216692A1 (de) * 2013-08-22 2015-02-26 Siemens Ag Österreich Verfahren zur Absicherung einer integrierten Schaltung gegen unberechtigte Zugriffe
JP6719894B2 (ja) 2015-12-04 2020-07-08 キヤノン株式会社 機能デバイス、制御装置
US20200004697A1 (en) * 2018-06-29 2020-01-02 Qualcomm Incorporated Patchable hardware for access control
TWI700605B (zh) * 2018-12-28 2020-08-01 新唐科技股份有限公司 安全晶片之時脈頻率攻擊偵測系統
US11182308B2 (en) * 2019-11-07 2021-11-23 Micron Technology, Inc. Semiconductor device with secure access key and associated methods and systems
US11809334B2 (en) * 2021-01-19 2023-11-07 Cirrus Logic Inc. Integrated circuit with asymmetric access privileges

Family Cites Families (22)

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GB2206431B (en) * 1987-06-30 1991-05-29 Motorola Inc Data card circuits
US5297268A (en) * 1988-06-03 1994-03-22 Dallas Semiconductor Corporation ID protected memory with a readable/writable ID template
US4991880A (en) 1989-08-28 1991-02-12 Handy And Harman Automotive Group, Inc. Quick connect coupling with twist release
JPH08153043A (ja) * 1994-11-28 1996-06-11 Sanyo Electric Co Ltd マイクロコンピュータの機密保持装置
US5838901A (en) * 1996-08-05 1998-11-17 Xilinx, Inc. Overridable data protection mechanism for PLDs
JPH11272560A (ja) * 1998-03-19 1999-10-08 Sony Corp 集積回路
FR2788353B1 (fr) * 1999-01-11 2001-02-23 St Microelectronics Sa Microprocesseur avec circuits de protection pour securiser l'acces a ses registres
JP2000215108A (ja) * 1999-01-22 2000-08-04 Toshiba Corp 半導体集積回路
DE60028379T2 (de) * 1999-03-30 2007-03-08 Siemens Energy & Automation, Inc. Speicherprogrammierbare steuerung
JP2001056848A (ja) * 1999-08-19 2001-02-27 Nec Corp Ｉｃコードのコマンド実行制御方法、ｉｃカード、ｉｃカードプログラムを記録した記録媒体
JP2001084160A (ja) * 1999-09-09 2001-03-30 Nec Corp マイクロコンピュータ及びその検査方法
US6998232B1 (en) * 1999-09-27 2006-02-14 Quark Biotech, Inc. Methods of diagnosing bladder cancer
US6487646B1 (en) * 2000-02-29 2002-11-26 Maxtor Corporation Apparatus and method capable of restricting access to a data storage device
JP4162846B2 (ja) * 2000-12-11 2008-10-08 沖電気工業株式会社 マイクロコンピュータ
US6640324B1 (en) * 2000-08-07 2003-10-28 Agere Systems Inc. Boundary scan chain routing
JP2002259927A (ja) * 2001-03-05 2002-09-13 Yoshikawa Rf System Kk データキャリア及びデータキャリアシステム
JP3898481B2 (ja) * 2001-10-03 2007-03-28 富士通株式会社 半導体記憶装置
DE10162308A1 (de) * 2001-12-19 2003-07-03 Philips Intellectual Property Verfahren und Anordnung zur Zugriffssteuerung auf EEPROMs sowie ein entsprechendes Computerprogrammprodukt und eine entsprechendes computerlesbares Speichermedium
TW539998B (en) * 2001-12-27 2003-07-01 Winbond Electronics Corp Computer booting device using smart card interface and the method thereof
JP2004094742A (ja) * 2002-09-02 2004-03-25 Sharp Corp データ処理装置
US7406333B2 (en) * 2002-11-15 2008-07-29 Motorola, Inc. Method and apparatus for operating a blocked secure storage memory
US7289382B2 (en) * 2003-12-23 2007-10-30 Intel Corporation Rewritable fuse memory

Also Published As

Publication number Publication date
TW200618259A (en) 2006-06-01
KR20070006806A (ko) 2007-01-11
EP1763715B1 (de) 2009-06-17
EP1763715A1 (de) 2007-03-21
CN100458643C (zh) 2009-02-04
TWI344690B (en) 2011-07-01
JP2007535050A (ja) 2007-11-29
CN1942844A (zh) 2007-04-04
ATE434228T1 (de) 2009-07-15
US20050242924A1 (en) 2005-11-03
WO2005106615A1 (en) 2005-11-10
KR100961807B1 (ko) 2010-06-08
JP4771550B2 (ja) 2011-09-14
US7274283B2 (en) 2007-09-25

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Legal Events

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8320 Willingness to grant licences declared (paragraph 23)
8364 No opposition during term of opposition