DE602005012682D1 - Leseverfahren für einen NAND-Speicher und NAND-Speichervorrichtung - Google Patents

Leseverfahren für einen NAND-Speicher und NAND-Speichervorrichtung

Info

Publication number
DE602005012682D1
DE602005012682D1 DE602005012682T DE602005012682T DE602005012682D1 DE 602005012682 D1 DE602005012682 D1 DE 602005012682D1 DE 602005012682 T DE602005012682 T DE 602005012682T DE 602005012682 T DE602005012682 T DE 602005012682T DE 602005012682 D1 DE602005012682 D1 DE 602005012682D1
Authority
DE
Germany
Prior art keywords
nand memory
reading method
memory device
nand
reading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005012682T
Other languages
English (en)
Inventor
Luca Crippa
Chiara Missiroli
Rino Micheloni
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
SK Hynix Inc
Original Assignee
STMicroelectronics SRL
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL, Hynix Semiconductor Inc filed Critical STMicroelectronics SRL
Publication of DE602005012682D1 publication Critical patent/DE602005012682D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
DE602005012682T 2005-07-22 2005-07-22 Leseverfahren für einen NAND-Speicher und NAND-Speichervorrichtung Active DE602005012682D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP05106782A EP1746605B1 (de) 2005-07-22 2005-07-22 Leseverfahren für einen NAND-Speicher und NAND-Speichervorrichtung

Publications (1)

Publication Number Publication Date
DE602005012682D1 true DE602005012682D1 (de) 2009-03-26

Family

ID=35462368

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005012682T Active DE602005012682D1 (de) 2005-07-22 2005-07-22 Leseverfahren für einen NAND-Speicher und NAND-Speichervorrichtung

Country Status (3)

Country Link
US (1) US7349265B2 (de)
EP (1) EP1746605B1 (de)
DE (1) DE602005012682D1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7518923B2 (en) 2006-12-29 2009-04-14 Sandisk Corporation Margined neighbor reading for non-volatile memory read operations including coupling compensation
US7606070B2 (en) * 2006-12-29 2009-10-20 Sandisk Corporation Systems for margined neighbor reading for non-volatile memory read operations including coupling compensation
KR100866961B1 (ko) * 2007-02-27 2008-11-05 삼성전자주식회사 불휘발성 메모리 장치 및 그 구동방법
KR20170073980A (ko) * 2015-12-21 2017-06-29 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그것의 동작 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6175522B1 (en) * 1999-09-30 2001-01-16 Advanced Micro Devices, Inc. Read operation scheme for a high-density, low voltage, and superior reliability nand flash memory device
JP4005761B2 (ja) * 2000-06-09 2007-11-14 株式会社東芝 半導体記憶装置
US6982905B2 (en) * 2003-10-09 2006-01-03 Micron Technology, Inc. Method and apparatus for reading NAND flash memory array
US7203092B2 (en) * 2005-05-12 2007-04-10 Micron Technology, Inc. Flash memory array using adjacent bit line as source
US7529131B2 (en) * 2005-11-11 2009-05-05 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory, method for reading out thereof, and memory card

Also Published As

Publication number Publication date
EP1746605A1 (de) 2007-01-24
EP1746605B1 (de) 2009-02-11
US20070047316A1 (en) 2007-03-01
US7349265B2 (en) 2008-03-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition