DE602005009937D1 - Extraktionsverfahren für die Lastverteilung in einem Halbleiterbauelement - Google Patents
Extraktionsverfahren für die Lastverteilung in einem HalbleiterbauelementInfo
- Publication number
- DE602005009937D1 DE602005009937D1 DE602005009937T DE602005009937T DE602005009937D1 DE 602005009937 D1 DE602005009937 D1 DE 602005009937D1 DE 602005009937 T DE602005009937 T DE 602005009937T DE 602005009937 T DE602005009937 T DE 602005009937T DE 602005009937 D1 DE602005009937 D1 DE 602005009937D1
- Authority
- DE
- Germany
- Prior art keywords
- charge
- semiconductor device
- pumping
- spatial
- distribution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
- G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
- G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Read Only Memory (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Die Bonding (AREA)
- Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US68707605P | 2005-06-03 | 2005-06-03 | |
US70485905P | 2005-08-01 | 2005-08-01 | |
EP05109600A EP1732080B1 (de) | 2005-06-03 | 2005-10-14 | Extraktionsverfahren für die Lastverteilung in einem Halbleiterbauelement |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602005009937D1 true DE602005009937D1 (de) | 2008-11-06 |
Family
ID=36975251
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602005009937T Active DE602005009937D1 (de) | 2005-06-03 | 2005-10-14 | Extraktionsverfahren für die Lastverteilung in einem Halbleiterbauelement |
DE602006009797T Active DE602006009797D1 (de) | 2005-06-03 | 2006-06-06 | Verfahren zum extrahieren der in einem halbleiterbauelement gespeicherten ladungsverteilung |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602006009797T Active DE602006009797D1 (de) | 2005-06-03 | 2006-06-06 | Verfahren zum extrahieren der in einem halbleiterbauelement gespeicherten ladungsverteilung |
Country Status (6)
Country | Link |
---|---|
US (2) | US7388785B2 (de) |
EP (2) | EP1732080B1 (de) |
JP (2) | JP5148076B2 (de) |
AT (2) | ATE409350T1 (de) |
DE (2) | DE602005009937D1 (de) |
WO (1) | WO2006128922A1 (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE602005019864D1 (de) * | 2005-06-03 | 2010-04-22 | Imec | Verfahren zur Steuerung einen nichtflüchtigen Ladungshaftstellen-Speicheranordnungen und Verfahren zur Bestimmung der Programmier-/Löschparameter |
US7482619B2 (en) * | 2005-09-07 | 2009-01-27 | Samsung Electronics Co., Ltd. | Charge trap memory device comprising composite of nanoparticles and method of fabricating the charge trap memory device |
US8394683B2 (en) | 2008-01-15 | 2013-03-12 | Micron Technology, Inc. | Methods of forming semiconductor constructions, and methods of forming NAND unit cells |
US8841682B2 (en) * | 2009-08-27 | 2014-09-23 | Cree, Inc. | Transistors with a gate insulation layer having a channel depleting interfacial charge and related fabrication methods |
US8941171B2 (en) * | 2010-07-02 | 2015-01-27 | Micron Technology, Inc. | Flatband voltage adjustment in a semiconductor device |
JP5801049B2 (ja) * | 2010-12-28 | 2015-10-28 | ラピスセミコンダクタ株式会社 | 半導体記憶装置へのデータの書込み方法及び半導体記憶装置 |
CN102163568B (zh) * | 2011-03-07 | 2012-10-10 | 北京大学 | 一种提取mos管沿沟道电荷分布的方法 |
US8832619B2 (en) * | 2013-01-28 | 2014-09-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Analytical model for predicting current mismatch in metal oxide semiconductor arrays |
EP3580776B1 (de) * | 2017-02-10 | 2021-04-28 | GlobalWafers Co., Ltd. | Verfahren zur beurteilung von halbleiterstrukturen |
KR20220026661A (ko) | 2020-08-25 | 2022-03-07 | 삼성디스플레이 주식회사 | 표시 장치 및 이의 구동 방법 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5583810A (en) | 1991-01-31 | 1996-12-10 | Interuniversitair Micro-Elektronica Centrum Vzw | Method for programming a semiconductor memory device |
JP3247396B2 (ja) * | 1991-03-29 | 2002-01-15 | 株式会社東芝 | 半導体装置の評価方法 |
IL125604A (en) * | 1997-07-30 | 2004-03-28 | Saifun Semiconductors Ltd | Non-volatile electrically erasable and programmble semiconductor memory cell utilizing asymmetrical charge |
US6768165B1 (en) | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US6331953B1 (en) | 2000-02-16 | 2001-12-18 | Advanced Micro Devices | Intelligent ramped gate and ramped drain erasure for non-volatile memory cells |
US6490204B2 (en) | 2000-05-04 | 2002-12-03 | Saifun Semiconductors Ltd. | Programming and erasing methods for a reference cell of an NROM array |
US6396741B1 (en) | 2000-05-04 | 2002-05-28 | Saifun Semiconductors Ltd. | Programming of nonvolatile memory cells |
US6928001B2 (en) | 2000-12-07 | 2005-08-09 | Saifun Semiconductors Ltd. | Programming and erasing methods for a non-volatile memory cell |
US6801453B2 (en) * | 2002-04-02 | 2004-10-05 | Macronix International Co., Ltd. | Method and apparatus of a read scheme for non-volatile memory |
KR100542701B1 (ko) | 2003-11-18 | 2006-01-11 | 주식회사 하이닉스반도체 | 낸드 플래시 메모리 소자의 문턱전압 측정 방법 |
US7151692B2 (en) * | 2004-01-27 | 2006-12-19 | Macronix International Co., Ltd. | Operation scheme for programming charge trapping non-volatile memory |
US7075828B2 (en) | 2004-04-26 | 2006-07-11 | Macronix International Co., Intl. | Operation scheme with charge balancing erase for charge trapping non-volatile memory |
US7345920B2 (en) | 2004-09-09 | 2008-03-18 | Macronix International Co., Ltd. | Method and apparatus for sensing in charge trapping non-volatile memory |
US20060113586A1 (en) * | 2004-11-29 | 2006-06-01 | Macronix International Co., Ltd. | Charge trapping dielectric structure for non-volatile memory |
JP2006196650A (ja) * | 2005-01-13 | 2006-07-27 | Sharp Corp | 半導体不揮発性メモリ装置およびその消去方法 |
DE602005019864D1 (de) | 2005-06-03 | 2010-04-22 | Imec | Verfahren zur Steuerung einen nichtflüchtigen Ladungshaftstellen-Speicheranordnungen und Verfahren zur Bestimmung der Programmier-/Löschparameter |
-
2005
- 2005-10-14 EP EP05109600A patent/EP1732080B1/de not_active Not-in-force
- 2005-10-14 DE DE602005009937T patent/DE602005009937D1/de active Active
- 2005-10-14 AT AT05109600T patent/ATE409350T1/de not_active IP Right Cessation
-
2006
- 2006-06-02 US US11/445,551 patent/US7388785B2/en active Active
- 2006-06-02 JP JP2006154455A patent/JP5148076B2/ja not_active Expired - Fee Related
- 2006-06-06 JP JP2008514128A patent/JP5191382B2/ja not_active Expired - Fee Related
- 2006-06-06 WO PCT/EP2006/062944 patent/WO2006128922A1/en active Application Filing
- 2006-06-06 EP EP06763541A patent/EP1886320B1/de not_active Not-in-force
- 2006-06-06 DE DE602006009797T patent/DE602006009797D1/de active Active
- 2006-06-06 AT AT06763541T patent/ATE445901T1/de not_active IP Right Cessation
- 2006-06-06 US US11/916,796 patent/US7933153B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP1732080B1 (de) | 2008-09-24 |
EP1886320A1 (de) | 2008-02-13 |
US20060284082A1 (en) | 2006-12-21 |
EP1732080A1 (de) | 2006-12-13 |
US20090135652A1 (en) | 2009-05-28 |
EP1886320B1 (de) | 2009-10-14 |
DE602006009797D1 (de) | 2009-11-26 |
ATE409350T1 (de) | 2008-10-15 |
JP5191382B2 (ja) | 2013-05-08 |
JP5148076B2 (ja) | 2013-02-20 |
US7933153B2 (en) | 2011-04-26 |
WO2006128922A1 (en) | 2006-12-07 |
US7388785B2 (en) | 2008-06-17 |
ATE445901T1 (de) | 2009-10-15 |
JP2006352111A (ja) | 2006-12-28 |
JP2008546194A (ja) | 2008-12-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |