DE602005019864D1 - Verfahren zur Steuerung einen nichtflüchtigen Ladungshaftstellen-Speicheranordnungen und Verfahren zur Bestimmung der Programmier-/Löschparameter - Google Patents
Verfahren zur Steuerung einen nichtflüchtigen Ladungshaftstellen-Speicheranordnungen und Verfahren zur Bestimmung der Programmier-/LöschparameterInfo
- Publication number
- DE602005019864D1 DE602005019864D1 DE602005019864T DE602005019864T DE602005019864D1 DE 602005019864 D1 DE602005019864 D1 DE 602005019864D1 DE 602005019864 T DE602005019864 T DE 602005019864T DE 602005019864 T DE602005019864 T DE 602005019864T DE 602005019864 D1 DE602005019864 D1 DE 602005019864D1
- Authority
- DE
- Germany
- Prior art keywords
- arrest
- controlling
- methods
- memory device
- determining program
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
- G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
- G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5002—Characteristic
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
- Circuits Of Receivers In General (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US68707605P | 2005-06-03 | 2005-06-03 | |
US70485905P | 2005-08-01 | 2005-08-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602005019864D1 true DE602005019864D1 (de) | 2010-04-22 |
Family
ID=41818466
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602005019864T Active DE602005019864D1 (de) | 2005-06-03 | 2005-10-14 | Verfahren zur Steuerung einen nichtflüchtigen Ladungshaftstellen-Speicheranordnungen und Verfahren zur Bestimmung der Programmier-/Löschparameter |
Country Status (5)
Country | Link |
---|---|
US (2) | US7508718B2 (de) |
EP (1) | EP1732081B1 (de) |
JP (1) | JP2006338863A (de) |
AT (1) | ATE460735T1 (de) |
DE (1) | DE602005019864D1 (de) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1732081B1 (de) * | 2005-06-03 | 2010-03-10 | Imec | Verfahren zur Steuerung einen nichtflüchtigen Ladungshaftstellen-Speicheranordnungen und Verfahren zur Bestimmung der Programmier-/Löschparameter |
ATE409350T1 (de) | 2005-06-03 | 2008-10-15 | Imec Inter Uni Micro Electr | Extraktionsverfahren für die lastverteilung in einem halbleiterbauelement |
US7482619B2 (en) * | 2005-09-07 | 2009-01-27 | Samsung Electronics Co., Ltd. | Charge trap memory device comprising composite of nanoparticles and method of fabricating the charge trap memory device |
JP4282702B2 (ja) * | 2006-09-22 | 2009-06-24 | 株式会社東芝 | 不揮発性半導体記憶装置 |
CN100590853C (zh) * | 2006-12-15 | 2010-02-17 | 中芯国际集成电路制造(上海)有限公司 | 半导体存储器及其形成方法 |
US8329535B2 (en) * | 2007-06-11 | 2012-12-11 | Macronix International Co., Ltd. | Multi-level-cell trapping DRAM |
KR101192358B1 (ko) * | 2007-07-31 | 2012-10-18 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 프로그래밍 방법 |
KR101551449B1 (ko) | 2009-02-25 | 2015-09-08 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 그것을 포함한 메모리 시스템 |
US7957188B2 (en) * | 2009-11-05 | 2011-06-07 | Fs Semiconductor Corp., Ltd. | Structures and methods of trimming threshold voltage of a flash EEPROM memory |
US8274828B2 (en) * | 2010-12-15 | 2012-09-25 | Fs Semiconductor Corp., Ltd. | Structures and methods for reading out non-volatile memory using referencing cells |
GB201322075D0 (en) | 2013-12-13 | 2014-01-29 | Ibm | Device for selecting a level for at least one read voltage |
US9251909B1 (en) | 2014-09-29 | 2016-02-02 | International Business Machines Corporation | Background threshold voltage shifting using base and delta threshold voltage shift values in flash memory |
US9563373B2 (en) | 2014-10-21 | 2017-02-07 | International Business Machines Corporation | Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management |
US10365859B2 (en) | 2014-10-21 | 2019-07-30 | International Business Machines Corporation | Storage array management employing a merged background management process |
US10339048B2 (en) | 2014-12-23 | 2019-07-02 | International Business Machines Corporation | Endurance enhancement scheme using memory re-evaluation |
US9990279B2 (en) | 2014-12-23 | 2018-06-05 | International Business Machines Corporation | Page-level health equalization |
CN111900199B (zh) * | 2017-07-18 | 2021-12-14 | 电子科技大学 | 栅极抽取和注入场效应晶体管载流子控制方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5583810A (en) * | 1991-01-31 | 1996-12-10 | Interuniversitair Micro-Elektronica Centrum Vzw | Method for programming a semiconductor memory device |
JP3417974B2 (ja) * | 1993-06-03 | 2003-06-16 | ローム株式会社 | 不揮発性記憶素子およびこれを利用した不揮発性記憶装置 |
US6768165B1 (en) * | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US6274898B1 (en) * | 1999-05-21 | 2001-08-14 | Vantis Corporation | Triple-well EEPROM cell using P-well for tunneling across a channel |
US6429063B1 (en) * | 1999-10-26 | 2002-08-06 | Saifun Semiconductors Ltd. | NROM cell with generally decoupled primary and secondary injection |
US6331953B1 (en) * | 2000-02-16 | 2001-12-18 | Advanced Micro Devices | Intelligent ramped gate and ramped drain erasure for non-volatile memory cells |
US6490204B2 (en) | 2000-05-04 | 2002-12-03 | Saifun Semiconductors Ltd. | Programming and erasing methods for a reference cell of an NROM array |
US6928001B2 (en) | 2000-12-07 | 2005-08-09 | Saifun Semiconductors Ltd. | Programming and erasing methods for a non-volatile memory cell |
US6396741B1 (en) * | 2000-05-04 | 2002-05-28 | Saifun Semiconductors Ltd. | Programming of nonvolatile memory cells |
TWI244165B (en) * | 2002-10-07 | 2005-11-21 | Infineon Technologies Ag | Single bit nonvolatile memory cell and methods for programming and erasing thereof |
JP4480955B2 (ja) * | 2003-05-20 | 2010-06-16 | シャープ株式会社 | 半導体記憶装置 |
KR100542701B1 (ko) * | 2003-11-18 | 2006-01-11 | 주식회사 하이닉스반도체 | 낸드 플래시 메모리 소자의 문턱전압 측정 방법 |
US7075828B2 (en) * | 2004-04-26 | 2006-07-11 | Macronix International Co., Intl. | Operation scheme with charge balancing erase for charge trapping non-volatile memory |
US7345920B2 (en) * | 2004-09-09 | 2008-03-18 | Macronix International Co., Ltd. | Method and apparatus for sensing in charge trapping non-volatile memory |
EP1732081B1 (de) * | 2005-06-03 | 2010-03-10 | Imec | Verfahren zur Steuerung einen nichtflüchtigen Ladungshaftstellen-Speicheranordnungen und Verfahren zur Bestimmung der Programmier-/Löschparameter |
ATE409350T1 (de) * | 2005-06-03 | 2008-10-15 | Imec Inter Uni Micro Electr | Extraktionsverfahren für die lastverteilung in einem halbleiterbauelement |
-
2005
- 2005-10-14 EP EP05109602A patent/EP1732081B1/de not_active Not-in-force
- 2005-10-14 DE DE602005019864T patent/DE602005019864D1/de active Active
- 2005-10-14 AT AT05109602T patent/ATE460735T1/de not_active IP Right Cessation
-
2006
- 2006-06-02 US US11/446,538 patent/US7508718B2/en not_active Expired - Fee Related
- 2006-06-02 JP JP2006154502A patent/JP2006338863A/ja active Pending
-
2009
- 2009-02-09 US US12/368,103 patent/US20090141563A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
EP1732081A1 (de) | 2006-12-13 |
US20060291287A1 (en) | 2006-12-28 |
US7508718B2 (en) | 2009-03-24 |
EP1732081B1 (de) | 2010-03-10 |
US20090141563A1 (en) | 2009-06-04 |
JP2006338863A (ja) | 2006-12-14 |
ATE460735T1 (de) | 2010-03-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |