DE602005004979D1 - Silizium-auf-Isolator Substrat, Verfahren zu seinetur - Google Patents

Silizium-auf-Isolator Substrat, Verfahren zu seinetur

Info

Publication number
DE602005004979D1
DE602005004979D1 DE602005004979T DE602005004979T DE602005004979D1 DE 602005004979 D1 DE602005004979 D1 DE 602005004979D1 DE 602005004979 T DE602005004979 T DE 602005004979T DE 602005004979 T DE602005004979 T DE 602005004979T DE 602005004979 D1 DE602005004979 D1 DE 602005004979D1
Authority
DE
Germany
Prior art keywords
silicon
insulator substrate
insulator
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE602005004979T
Other languages
English (en)
Other versions
DE602005004979T2 (de
Inventor
Seok-Whan Chung
Hyung Choi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE602005004979D1 publication Critical patent/DE602005004979D1/de
Application granted granted Critical
Publication of DE602005004979T2 publication Critical patent/DE602005004979T2/de
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
    • B81C1/00563—Avoid or control over-etching
    • B81C1/00579—Avoid charge built-up
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0128—Processes for removing material
    • B81C2201/013—Etching
    • B81C2201/0132—Dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Micromachines (AREA)
  • Element Separation (AREA)
  • Gyroscopes (AREA)
DE602005004979T 2004-10-20 2005-10-12 Silizium-auf-Isolator Substrat, Verfahren zu seiner Herstellung und darin geformte MEMS Schwingstruktur Expired - Fee Related DE602005004979T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020040083855A KR100605368B1 (ko) 2004-10-20 2004-10-20 Ｓｏｉ기판, 그 제조방법, 그리고, 그 ｓｏｉ기판을이용한 부유 구조체 제조 방법
KR2004083855 2004-10-20

Publications (2)

Publication Number Publication Date
DE602005004979D1 true DE602005004979D1 (de) 2008-04-10
DE602005004979T2 DE602005004979T2 (de) 2009-03-12

Family

ID=35746799

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005004979T Expired - Fee Related DE602005004979T2 (de) 2004-10-20 2005-10-12 Silizium-auf-Isolator Substrat, Verfahren zu seiner Herstellung und darin geformte MEMS Schwingstruktur

Country Status (5)

Country Link
US (1) US7208800B2 (de)
EP (1) EP1650158B1 (de)
JP (1) JP2006121092A (de)
KR (1) KR100605368B1 (de)
DE (1) DE602005004979T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006002753B4 (de) * 2006-01-20 2010-09-30 X-Fab Semiconductor Foundries Ag Verfahren und Anordnung zur Bewertung der Unterätzung von tiefen Grabenstrukturen in SOI-Scheiben
US20090282917A1 (en) * 2008-05-19 2009-11-19 Cenk Acar Integrated multi-axis micromachined inertial sensing unit and method of fabrication
US8648432B2 (en) * 2011-11-28 2014-02-11 Texas Instruments Deutschland Gmbh Fully embedded micromechanical device, system on chip and method for manufacturing the same
US8877605B1 (en) 2013-04-11 2014-11-04 Eastman Kodak Company Silicon substrate fabrication

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5050105A (en) 1988-01-26 1991-09-17 International Business Machines Corporation Direct cursor-controlled access to multiple application programs and data
US5177661A (en) 1989-01-13 1993-01-05 Kopin Corporation SOI diaphgram sensor
JPH0529214A (ja) * 1991-07-18 1993-02-05 Sharp Corp 半導体基板の製造方法
JPH05234884A (ja) * 1992-02-20 1993-09-10 Fujitsu Ltd 半導体装置の製造方法
JPH05251292A (ja) * 1992-03-06 1993-09-28 Nec Corp 半導体装置の製造方法
US6287885B1 (en) * 1998-05-08 2001-09-11 Denso Corporation Method for manufacturing semiconductor dynamic quantity sensor
KR100304713B1 (ko) * 1999-10-12 2001-11-02 윤종용 부분적인 ｓｏｉ 구조를 갖는 반도체소자 및 그 제조방법
US6755982B2 (en) * 2002-01-07 2004-06-29 Xerox Corporation Self-aligned micro hinges
US6916728B2 (en) * 2002-12-23 2005-07-12 Freescale Semiconductor, Inc. Method for forming a semiconductor structure through epitaxial growth
US7122395B2 (en) 2002-12-23 2006-10-17 Motorola, Inc. Method of forming semiconductor devices through epitaxy
JP4238724B2 (ja) * 2003-03-27 2009-03-18 株式会社デンソー 半導体装置

Also Published As

Publication number Publication date
US20060081929A1 (en) 2006-04-20
DE602005004979T2 (de) 2009-03-12
US7208800B2 (en) 2007-04-24
KR20060034849A (ko) 2006-04-26
JP2006121092A (ja) 2006-05-11
EP1650158A1 (de) 2006-04-26
KR100605368B1 (ko) 2006-07-28
EP1650158B1 (de) 2008-02-27

Similar Documents

Publication Publication Date Title
ATE428818T1 (de) Verfahren zum bleichen von substraten
DE602007001549D1 (de) Substrathaltevorrichtung
DE602005026918D1 (de) Techniken zur reduzierung von substrat-nebensprech
DE502005003910D1 (de) Verfahren zur modifizierung faserartiger substrate mit siloxancopolymeren
DE602005024119D1 (de) Verfahren zum allergennachweis
DE602005007508D1 (de) Funktioneller zuckerersatz
FI20060288A0 (fi) Pinnoitusmenetelmä
DE602007013995D1 (de) Beschichtungsverfahren
DE502005010287D1 (de) Verfahren zur hydrocyanierung
DE602005023445D1 (de) Malverfahren
TWI318697B (en) Large substrate test system
FR2868684B1 (fr) Lingettes antibuee
DE602006012689D1 (de) Überprüfungsverfahren
DE602006009027D1 (de) Piezoelektrisches Substrat und Verfahren zu dessen Herstellung
DE602005004979D1 (de) Silizium-auf-Isolator Substrat, Verfahren zu seinetur
FR2914493B1 (fr) Substrat demontable.
DK1717311T3 (da) Fremgangsmåde til fremstilling af lactoperoxidase
DK1955066T3 (da) Membran-assay-fremgangsmåde
NO20040634D0 (no) En smiprosess
DE602006004709D1 (de) Beschichtungsverfahren
ATE378433T1 (de) Haldenbioauslaugungsverfahren
DE102004058335A8 (de) Substrat
ITMI20040132A1 (it) Processo per preparare fluoroalogenoeteri
AT7072U3 (de) Umbauverfahren
DE502005006485D1 (de) Verfahren zum verbinden von bauteilen

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee