DE602004022141D1 - Mehrfachbelichtungsverfahren zur schaltungsleistungsverbesserung und maskenset - Google Patents

Mehrfachbelichtungsverfahren zur schaltungsleistungsverbesserung und maskenset

Info

Publication number
DE602004022141D1
DE602004022141D1 DE602004022141T DE602004022141T DE602004022141D1 DE 602004022141 D1 DE602004022141 D1 DE 602004022141D1 DE 602004022141 T DE602004022141 T DE 602004022141T DE 602004022141 T DE602004022141 T DE 602004022141T DE 602004022141 D1 DE602004022141 D1 DE 602004022141D1
Authority
DE
Germany
Prior art keywords
exposure method
circuit power
multiple exposure
mask set
power improvement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004022141T
Other languages
English (en)
Inventor
Jun Wang
K Alfred Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Hong Kong HKU
Original Assignee
University of Hong Kong HKU
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Hong Kong HKU filed Critical University of Hong Kong HKU
Publication of DE602004022141D1 publication Critical patent/DE602004022141D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
DE602004022141T 2003-02-27 2004-02-27 Mehrfachbelichtungsverfahren zur schaltungsleistungsverbesserung und maskenset Expired - Lifetime DE602004022141D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US45049603P 2003-02-27 2003-02-27
PCT/CN2004/000149 WO2004077162A1 (en) 2003-02-27 2004-02-27 Multiple exposure method for circuit performance improvement

Publications (1)

Publication Number Publication Date
DE602004022141D1 true DE602004022141D1 (de) 2009-09-03

Family

ID=32927660

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004022141T Expired - Lifetime DE602004022141D1 (de) 2003-02-27 2004-02-27 Mehrfachbelichtungsverfahren zur schaltungsleistungsverbesserung und maskenset

Country Status (6)

Country Link
US (1) US20040229135A1 (de)
EP (1) EP1597631B1 (de)
JP (1) JP2006519480A (de)
CN (1) CN100498532C (de)
DE (1) DE602004022141D1 (de)
WO (1) WO2004077162A1 (de)

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US7465525B2 (en) * 2005-05-10 2008-12-16 Lam Research Corporation Reticle alignment and overlay for multiple reticle process
US7539969B2 (en) * 2005-05-10 2009-05-26 Lam Research Corporation Computer readable mask shrink control processor
US7271108B2 (en) * 2005-06-28 2007-09-18 Lam Research Corporation Multiple mask process with etch mask stack
US20070087291A1 (en) * 2005-10-18 2007-04-19 Taiwan Semiconductor Manufacturing Co., Ltd. Lithography process to reduce interference
US7493589B2 (en) * 2005-12-29 2009-02-17 Asml Masktools B.V. Method, program product and apparatus for model based geometry decomposition for use in a multiple exposure process
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8245180B2 (en) 2006-03-09 2012-08-14 Tela Innovations, Inc. Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8225239B2 (en) * 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining and utilizing sub-resolution features in linear topology
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US8225261B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining contact grid in dynamic array architecture
US8247846B2 (en) 2006-03-09 2012-08-21 Tela Innovations, Inc. Oversized contacts and vias in semiconductor chip defined by linearly constrained topology
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US7519941B2 (en) 2006-04-13 2009-04-14 International Business Machines Corporation Method of manufacturing integrated circuits using pre-made and pre-qualified exposure masks for selected blocks of circuitry
DE102006018928A1 (de) 2006-04-24 2007-11-08 Carl Zeiss Smt Ag Projektionsbelichtungssystem und Verwendung desselben
JP2008076683A (ja) * 2006-09-20 2008-04-03 Canon Inc 原版データ作成プログラム、原版データ作成方法、原版作成方法、露光方法及びデバイスの製造方法
US8286107B2 (en) 2007-02-20 2012-10-09 Tela Innovations, Inc. Methods and systems for process compensation technique acceleration
US7888705B2 (en) 2007-08-02 2011-02-15 Tela Innovations, Inc. Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US7562326B2 (en) * 2007-08-09 2009-07-14 United Microelectronics Corp. Method of generating a standard cell layout and transferring the standard cell layout to a substrate
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US8173544B2 (en) * 2008-05-02 2012-05-08 Texas Instruments Incorporated Integrated circuit having interleaved gridded features, mask set and method for printing
JP5120100B2 (ja) * 2008-06-23 2013-01-16 富士通セミコンダクター株式会社 半導体装置の製造方法及びレチクルの形成方法
SG10201608214SA (en) 2008-07-16 2016-11-29 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
KR101828492B1 (ko) * 2010-10-13 2018-03-29 삼성전자 주식회사 패턴 형성 방법, 레티클, 및 패턴 형성 프로그램이 기록된 기록 매체
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US8530121B2 (en) * 2012-02-08 2013-09-10 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-grid exposure method
USD729808S1 (en) * 2013-03-13 2015-05-19 Nagrastar Llc Smart card interface
USD759022S1 (en) * 2013-03-13 2016-06-14 Nagrastar Llc Smart card interface
USD758372S1 (en) 2013-03-13 2016-06-07 Nagrastar Llc Smart card interface
CN104346490B (zh) * 2013-08-09 2017-10-10 复旦大学 一种三重曝光光刻工艺的版图图案分解方法
USD780763S1 (en) * 2015-03-20 2017-03-07 Nagrastar Llc Smart card interface
USD864968S1 (en) 2015-04-30 2019-10-29 Echostar Technologies L.L.C. Smart card interface
US11055464B2 (en) 2018-08-14 2021-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Critical dimension uniformity

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US5563012A (en) * 1994-06-30 1996-10-08 International Business Machines Corporation Multi mask method for selective mask feature enhancement
US5652084A (en) * 1994-12-22 1997-07-29 Cypress Semiconductor Corporation Method for reduced pitch lithography
KR100346448B1 (ko) * 1994-12-29 2002-11-23 주식회사 하이닉스반도체 반도체소자용노광마스크
JPH117120A (ja) * 1997-06-18 1999-01-12 Sony Corp マスクパターン作成方法およびマスクパターン作成装置並びにマスク作成装置
JPH11133585A (ja) * 1997-10-30 1999-05-21 Nec Corp 露光用マスク及びその製造方法
JP3119217B2 (ja) * 1997-10-31 2000-12-18 日本電気株式会社 フォトマスクおよびフォトマスクを使用した露光方法
US6114071A (en) * 1997-11-24 2000-09-05 Asml Masktools Netherlands B.V. Method of fine feature edge tuning with optically-halftoned mask
US6518180B1 (en) * 1998-10-23 2003-02-11 Hitachi, Ltd. Method for fabricating semiconductor device and method for forming mask suitable therefor
DE19937742B4 (de) * 1999-08-10 2008-04-10 Infineon Technologies Ag Übertragung eines Musters hoher Strukturdichte durch multiple Belichtung weniger dichter Teilmuster
JP2001110719A (ja) * 1999-10-14 2001-04-20 Hitachi Ltd 露光方法
JP4145003B2 (ja) * 2000-07-14 2008-09-03 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US20050136340A1 (en) * 2000-07-21 2005-06-23 Asml Netherlands B.V. Lithographic apparatus and methods, patterning structure and method for making a patterning structure, device manufacturing method, and device manufactured thereby
JP3768794B2 (ja) * 2000-10-13 2006-04-19 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US6541166B2 (en) * 2001-01-18 2003-04-01 International Business Machines Corporation Method and apparatus for lithographically printing tightly nested and isolated device features using multiple mask exposures
US6553562B2 (en) * 2001-05-04 2003-04-22 Asml Masktools B.V. Method and apparatus for generating masks utilized in conjunction with dipole illumination techniques
JP4235410B2 (ja) * 2002-08-01 2009-03-11 キヤノン株式会社 露光方法

Also Published As

Publication number Publication date
CN1754131A (zh) 2006-03-29
EP1597631B1 (de) 2009-07-22
US20040229135A1 (en) 2004-11-18
CN100498532C (zh) 2009-06-10
EP1597631A4 (de) 2006-09-13
WO2004077162A1 (en) 2004-09-10
EP1597631A1 (de) 2005-11-23
JP2006519480A (ja) 2006-08-24

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