DE602004007906D1 - Testeinrichtung und einstellverfahren - Google Patents

Testeinrichtung und einstellverfahren

Info

Publication number
DE602004007906D1
DE602004007906D1 DE602004007906T DE602004007906T DE602004007906D1 DE 602004007906 D1 DE602004007906 D1 DE 602004007906D1 DE 602004007906 T DE602004007906 T DE 602004007906T DE 602004007906 T DE602004007906 T DE 602004007906T DE 602004007906 D1 DE602004007906 D1 DE 602004007906D1
Authority
DE
Germany
Prior art keywords
test device
adjustment procedure
procedure
adjustment
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004007906T
Other languages
English (en)
Other versions
DE602004007906T2 (de
Inventor
Takeshi Yaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Publication of DE602004007906D1 publication Critical patent/DE602004007906D1/de
Application granted granted Critical
Publication of DE602004007906T2 publication Critical patent/DE602004007906T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE602004007906T 2003-03-19 2004-03-16 Testeinrichtung und einstellverfahren Expired - Lifetime DE602004007906T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2003074898 2003-03-19
JP2003074898 2003-03-19
PCT/JP2004/003456 WO2004083879A1 (ja) 2003-03-19 2004-03-16 試験装置及び設定方法

Publications (2)

Publication Number Publication Date
DE602004007906D1 true DE602004007906D1 (de) 2007-09-13
DE602004007906T2 DE602004007906T2 (de) 2008-04-10

Family

ID=33027852

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004007906T Expired - Lifetime DE602004007906T2 (de) 2003-03-19 2004-03-16 Testeinrichtung und einstellverfahren

Country Status (9)

Country Link
US (2) US7107172B2 (de)
EP (1) EP1612572B1 (de)
JP (1) JP4520942B2 (de)
KR (1) KR20050109548A (de)
CN (1) CN100445761C (de)
DE (1) DE602004007906T2 (de)
MY (2) MY146849A (de)
TW (1) TWI317817B (de)
WO (1) WO2004083879A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2011001462A1 (ja) * 2009-06-29 2012-12-10 株式会社アドバンテスト 試験装置
US8547125B2 (en) 2010-01-26 2013-10-01 Advantest Corporation Test apparatus and test module
CN104730448B (zh) * 2013-12-20 2017-07-28 致茂电子股份有限公司 自动测试设备资源配置方法与自动测试通道配置装置
CN104764942B (zh) * 2014-01-02 2018-08-14 致茂电子股份有限公司 自动测试设备及其控制方法
TWI588504B (zh) * 2015-12-23 2017-06-21 致茂電子股份有限公司 自動測試通道配置裝置及其控制方法
CN106019120B (zh) * 2016-05-12 2018-12-04 中国电子科技集团公司第四十一研究所 基于可扩展器件测试库的测试管理方法
CN109507569A (zh) * 2018-12-20 2019-03-22 深圳市长龙铁路电子工程有限公司 一种机车信号车载设备解码板的io测试方法
CN111208380A (zh) * 2020-04-17 2020-05-29 北京全路通信信号研究设计院集团有限公司 一种轨道电路室外设备测试装置、系统及方法
JP2022044114A (ja) * 2020-09-07 2022-03-17 キオクシア株式会社 半導体集積回路およびその試験方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4070565A (en) * 1976-08-18 1978-01-24 Zehntel, Inc. Programmable tester method and apparatus
US5390129A (en) * 1992-07-06 1995-02-14 Motay Electronics, Inc. Universal burn-in driver system and method therefor
JPH07218602A (ja) 1994-02-07 1995-08-18 Advantest Corp 半導体試験装置
US5805610A (en) * 1997-04-28 1998-09-08 Credence Systems Corporation Virtual channel data distribution system for integrated circuit tester
US6374379B1 (en) * 1999-02-05 2002-04-16 Teradyne, Inc. Low-cost configuration for monitoring and controlling parametric measurement units in automatic test equipment
US6557128B1 (en) * 1999-11-12 2003-04-29 Advantest Corp. Semiconductor test system supporting multiple virtual logic testers
US6567941B1 (en) * 2000-04-12 2003-05-20 Advantest Corp. Event based test system storing pin calibration data in non-volatile memory
JP2002062340A (ja) * 2000-08-23 2002-02-28 Toshiba Corp 半導体試験装置
US7003697B2 (en) * 2001-07-02 2006-02-21 Nextest Systems, Corporation Apparatus having pattern scrambler for testing a semiconductor device and method for operating same
US6885961B2 (en) * 2002-02-28 2005-04-26 Teradyne, Inc. Hybrid tester architecture
US6941232B2 (en) * 2003-01-28 2005-09-06 Texas Instruments Incorporated Method and apparatus for performing multi-site integrated circuit device testing
KR20060009951A (ko) * 2003-05-21 2006-02-01 주식회사 아도반테스토 시험 장치 및 테스트 모듈

Also Published As

Publication number Publication date
WO2004083879A1 (ja) 2004-09-30
JPWO2004083879A1 (ja) 2006-06-22
MY146074A (en) 2012-06-29
KR20050109548A (ko) 2005-11-21
CN1761885A (zh) 2006-04-19
CN100445761C (zh) 2008-12-24
US20040220763A1 (en) 2004-11-04
US20060212252A1 (en) 2006-09-21
JP4520942B2 (ja) 2010-08-11
MY146849A (en) 2012-09-28
EP1612572B1 (de) 2007-08-01
EP1612572A1 (de) 2006-01-04
TW200428009A (en) 2004-12-16
TWI317817B (en) 2009-12-01
DE602004007906T2 (de) 2008-04-10
EP1612572A4 (de) 2006-04-19
US7107172B2 (en) 2006-09-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition