DE602004005669D1 - N-Domino Ausgangskippschaltung mit schnellem Auswertepfad - Google Patents

N-Domino Ausgangskippschaltung mit schnellem Auswertepfad

Info

Publication number
DE602004005669D1
DE602004005669D1 DE602004005669T DE602004005669T DE602004005669D1 DE 602004005669 D1 DE602004005669 D1 DE 602004005669D1 DE 602004005669 T DE602004005669 T DE 602004005669T DE 602004005669 T DE602004005669 T DE 602004005669T DE 602004005669 D1 DE602004005669 D1 DE 602004005669D1
Authority
DE
Germany
Prior art keywords
flop
output flip
fast evaluation
evaluation path
domino output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004005669T
Other languages
English (en)
Other versions
DE602004005669T2 (de
Inventor
Raymond A Bertram
James R Lundberg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Via Technologies Inc
Original Assignee
Via Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Technologies Inc filed Critical Via Technologies Inc
Publication of DE602004005669D1 publication Critical patent/DE602004005669D1/de
Application granted granted Critical
Publication of DE602004005669T2 publication Critical patent/DE602004005669T2/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
DE602004005669T 2004-04-28 2004-09-14 N-Domino Ausgangskippschaltung mit schnellem Auswertepfad Active DE602004005669T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US833493 2004-04-28
US10/833,493 US7034578B2 (en) 2003-04-28 2004-04-28 N-domino output latch with accelerated evaluate path

Publications (2)

Publication Number Publication Date
DE602004005669D1 true DE602004005669D1 (de) 2007-05-16
DE602004005669T2 DE602004005669T2 (de) 2007-12-13

Family

ID=34930653

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004005669T Active DE602004005669T2 (de) 2004-04-28 2004-09-14 N-Domino Ausgangskippschaltung mit schnellem Auswertepfad

Country Status (5)

Country Link
US (1) US7034578B2 (de)
EP (1) EP1592133B1 (de)
CN (1) CN1667954B (de)
DE (1) DE602004005669T2 (de)
TW (1) TWI289003B (de)

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US20040019923A1 (en) * 1997-10-16 2004-01-29 Ivarie Robert D. Exogenous proteins expressed in avians and their eggs
US7187211B2 (en) * 2002-08-14 2007-03-06 Via Technologies, Inc. P-domino output latch
US7193445B2 (en) * 2002-08-14 2007-03-20 Ip-First, Llc Non-inverting domino register
US7187209B2 (en) * 2003-08-13 2007-03-06 Via Technologies, Inc. Non-inverting domino register
US7417465B2 (en) * 2002-08-14 2008-08-26 Via Technologies, Inc. N-domino output latch
US7084464B2 (en) * 2003-07-10 2006-08-01 Stmicroelectronics, Inc. Library of cells for use in designing sets of domino logic circuits in a standard cell library, or the like, and method for using same
US7187210B2 (en) 2003-08-13 2007-03-06 Via Technologies, Inc. P-domino register
US7405597B1 (en) 2005-06-30 2008-07-29 Transmeta Corporation Advanced repeater with duty cycle adjustment
US7498846B1 (en) 2004-06-08 2009-03-03 Transmeta Corporation Power efficient multiplexer
US7304503B2 (en) 2004-06-08 2007-12-04 Transmeta Corporation Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability
US7336103B1 (en) * 2004-06-08 2008-02-26 Transmeta Corporation Stacked inverter delay chain
US7142018B2 (en) * 2004-06-08 2006-11-28 Transmeta Corporation Circuits and methods for detecting and assisting wire transitions
US7071747B1 (en) 2004-06-15 2006-07-04 Transmeta Corporation Inverting zipper repeater circuit
US7330080B1 (en) 2004-11-04 2008-02-12 Transmeta Corporation Ring based impedance control of an output driver
US20060139061A1 (en) * 2004-12-27 2006-06-29 Curtis Steve M Protected set dominant latch
US7358775B2 (en) * 2005-01-14 2008-04-15 Via Technologies, Inc. Inverting dynamic register with data-dependent hold time reduction mechanism
US7663408B2 (en) * 2005-06-30 2010-02-16 Robert Paul Masleid Scannable dynamic circuit latch
US7394681B1 (en) 2005-11-14 2008-07-01 Transmeta Corporation Column select multiplexer circuit for a domino random access memory array
US7414485B1 (en) 2005-12-30 2008-08-19 Transmeta Corporation Circuits, systems and methods relating to dynamic ring oscillators
TWI337002B (en) * 2006-01-15 2011-02-01 Via Tech Inc Inverting dynamic register with data-dependent hold time reduction mechanism
US7317339B1 (en) * 2006-06-16 2008-01-08 Via Technologies, Inc. N-domino register with accelerated non-discharge path
US7321243B1 (en) * 2006-06-16 2008-01-22 Via Technologies, Inc. P-domino register with accelerated non-charge path
US7710153B1 (en) 2006-06-30 2010-05-04 Masleid Robert P Cross point switch
US7495466B1 (en) * 2006-06-30 2009-02-24 Transmeta Corporation Triple latch flip flop system and method
US7382161B2 (en) * 2006-08-11 2008-06-03 Via Technologies, Inc. Accelerated P-channel dynamic register
US7348806B2 (en) 2006-08-11 2008-03-25 Via Technologies, Inc. Accelerated N-channel dynamic register
US7372305B1 (en) * 2006-10-31 2008-05-13 International Business Machines Corporation Scannable dynamic logic latch circuit
US7639057B1 (en) * 2006-12-07 2009-12-29 Marvell International Ltd. Clock gater system
US7990180B2 (en) * 2009-09-09 2011-08-02 Via Technologies, Inc. Fast dynamic register
KR101730870B1 (ko) * 2010-12-06 2017-04-28 삼성전자주식회사 도미노 로직 회로 및 파이프라인 도미노 로직 회로
US8890573B2 (en) * 2012-09-07 2014-11-18 Nvidia Corporation Clock gating latch, method of operation thereof and integrated circuit employing the same
US10581410B2 (en) * 2015-09-10 2020-03-03 Samsung Electronics Co., Ltd High speed domino-based flip flop
CN107634732B (zh) * 2017-11-06 2023-10-20 长鑫存储技术有限公司 一种时间放大器以及半导体存储器

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US5045721A (en) * 1989-03-16 1991-09-03 Teledyne Industries Zero static current high speed TTL compatible buffer
US5453708A (en) * 1995-01-04 1995-09-26 Intel Corporation Clocking scheme for latching of a domino output
US5568069A (en) * 1995-02-27 1996-10-22 Hughes Aircraft Company High speed, low power pipelined logic circuit
US5642061A (en) * 1995-04-17 1997-06-24 Hitachi America, Ltd. Short circuit current free dynamic logic clock timing
US5867036A (en) * 1996-05-29 1999-02-02 Lsi Logic Corporation Domino scan architecture and domino scan flip-flop for the testing of domino and hybrid CMOS circuits
US5926038A (en) * 1997-11-10 1999-07-20 The United States Of America As Represented By The Secretary Of The Navy Two-phase dynamic logic circuits for gallium arsenide complementary HIGFET fabrication
US6060909A (en) * 1998-04-21 2000-05-09 International Business Machines Corporation Compound domino logic circuit including an output driver section with a latch
US6058403A (en) * 1998-08-06 2000-05-02 Intel Corporation Broken stack priority encoder
JP3241686B2 (ja) * 1999-03-26 2001-12-25 日本電気株式会社 ダイナミック型論理回路及びドミノ論理素子
US6271684B1 (en) * 1999-04-08 2001-08-07 Intel Corporation Method and apparatus for stalling OTB domino circuits
US6201415B1 (en) * 1999-08-05 2001-03-13 Intel Corporation Latched time borrowing domino circuit
US6377078B1 (en) * 1999-12-30 2002-04-23 Intel Corporation Circuit to reduce charge sharing for domino circuits with pulsed clocks
JP3533357B2 (ja) 2000-02-29 2004-05-31 株式会社東芝 論理演算機能を備えた半導体集積回路
US6420904B1 (en) * 2001-01-25 2002-07-16 Koninklijke Philips Electronics N.V. Domino logic with self-timed precharge
US6732336B2 (en) * 2001-10-11 2004-05-04 California Institute Of Technology Method and apparatus for an asynchronous pulse logic circuit
US6677783B2 (en) * 2001-12-31 2004-01-13 Intel Corporation High-speed, state-preserving, race-reducing, wide-pulsed-clock domino design style

Also Published As

Publication number Publication date
US7034578B2 (en) 2006-04-25
TWI289003B (en) 2007-10-21
CN1667954A (zh) 2005-09-14
EP1592133A1 (de) 2005-11-02
US20040257115A1 (en) 2004-12-23
EP1592133B1 (de) 2007-04-04
TW200536264A (en) 2005-11-01
DE602004005669T2 (de) 2007-12-13
CN1667954B (zh) 2010-05-12

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