TWI337002B - Inverting dynamic register with data-dependent hold time reduction mechanism - Google Patents

Description

1337002 CNTR2202 21757t\vf.doc/e After the introduction of the traditional register circuit, the cumulative effect of the pipeline system is greatly reduced when the pipeline system introduces a delay. Specifically, it is worth noting that these delays are derived from the logic evaluation circuit and must meet the set time requirements to ensure a stable scratch output. It is desirable to reduce these delays to provide additional time at each stage to increase the overall speed of the pipeline system. Used to reduce the setting and clock output delay gambling, - η. The technique of cutting e _flgUrati (4) usually = to increase the time. In particular, the #龙龙时时脉人到到暂路日ί, the state of the input data must be in a specific period (that is, the holding remains unchanged. If it changes before the end of the holding time, the temporary storage benefit may be It is not correct. *The second phase of the traditional domino-type circuit needs to maintain the time circuit's need for holding time. Many of the low-class traditional sapwoods (ie, the clock signal), from the duration; Compared with the non-clock state, the state is greatly shortened. Nowadays f = 'its "clock", the state signal, its corresponding clock state only accounts for less than the second clock, therefore, it is also necessary to provide a temporary currency, The requirement of holding time is greatly reduced, and the sub-set and method depend on the requirement of providing the corresponding pulse-type clock signal to maintain the time. [Inventive content j & 丨 本 发 发 ψ ψ ψ , , , , Dedicated to other problems, shortcomings and problems of the prior art: 1337002 CNTR2202 21757twf.d〇c/e The present invention provides a better technique for reducing the hold time requirement for temporary storage logic. In the example, provide - type ^ Dynamic logic register. The inverting dynamic logic register includes: - a mutual evaluation, set, evaluation logic unit, delay logic unit, and flash lock logic single complement evaluation device in response to the clock signal. Evaluation logic unit connection, complementary The pre-charging node between the evaluation devices. The evaluation logic evaluates the logic function according to the less-input data signal, and the two-dimensional state is the first state or the second state. The delay logic unit and the clock=time , the delay between the pulse and the truncation signal = coincidence; when the function value is the first state, the time heart 2 is maintained; to: the =, the truncation signal and the pre-charge node between the periods, the edge The evaluation unit of the evaluation node between the next edge of the truncation signal controls the output according to the state of the pre-charging node, that is, the point of the sorrow, the sorrow output node is in a three-state state. The device type dynamic temporary storage 11 circuit ί 雷 雷 匕 Bi / H 'delay logic circuit 'Qlock circuit and keep: « When the clock signal is low, the dynamic electric pre-pulse signal becomes high _, = j = state ' and the current receiving clock signal, Delayed logic electrical clock signal, in which the clock signal is short with two == late. _ way and dynamic circuit and: logic == 1337002 CNTR2202 21757twf.doc/e clock signal becomes high power to stop During the evaluation period during which the money becomes high, the state of the output node is controlled according to the state of the first node, otherwise the output node is in a tristate state. The keeper circuit is connected to the output node. The other aspect of the invention includes dynamic temporary storage output signal The method includes: when the current pulse signal is in the first logic state, setting the first node when the current pulse signal is converted into the second logic state, the dynamic evaluation logic function is the second state of the first shape to control the first The logical separation of the nodes;

= late clock signal, and provides a truncation signal, wherein the truncated signal is a delayed clock signal; when the logic function is evaluated as the first state, the signal is added; according to the time when the pulse is converted into the third logic state Ending under the truncation signal - the evaluation period of the corresponding transition, determining the logical departure of the first node, the lock output throttling logic state; and the logic state of the input point during the evaluation cycle. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following description is made to enable those skilled in the art to grasp the invention and the specific application environment and requirements provided by the present invention. However, it is obvious that the skilled person can modify the preferred embodiment, and the general principles defined herein are still turned to other embodiments. Therefore, the present invention is not limited to the specific implementations described herein, but should be related to the principles and new directivity of the present invention. The inventors of the present application have recognized the need to provide a temporary storage for the logic circuit, where speed is a key factor and also requires an excellent: overall; 'If you increase the speed by reducing the number of devices and reduce the chip area ^ In addition, you have realized that you need a more robust (r〇bust) logic circuit, which has 1337002 CNTR2202 21757twf.doc/e temporary rim 'rhyme The turn-time _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Therefore, 'dynamic logic temporary storage, and method' have been developed to provide _-type and temporary storage for the evaluation function, which is significantly faster than the (4) structure, which minimizes the time-keeping requirements of certain wheel sets. And the bean into the heart: there is a significant reduction in the heart. And it is more than the current 7 device (four) pulse output

When the data is transferred from the level to the other stage using the register is greatly dependent on the scratchpad, the actual operation speed of the whole device is greatly improved, and the wafer layout area is reduced. In addition, the design is more robust due to lower retention time requirements. 1 is a schematic diagram of a prior art dynamic circuit 100 for representing today's dynamic circuit techniques. Those skilled in the art also refer to this dynamic circuit 100 as a domino circuit 100 or a domino logic. The dynamic circuit 1GG includes an input portion which is composed of a stacked p-channel and an N-channel device, and a pair of complementary evaluation devices, and the N1 is an evaluation logic unit. The source of ρι is connected to the power supply voltage VDD' and the & pole is connected to node 1G5 to provide a signal. The drain of HPN1 is connected to node 1〇5, and its source is connected to the drain of N2. The source of N2 is grounded. The input clock signal is supplied to the gates of P1 and N2 through node 1〇1. The input data signal Data is supplied to the gate of N1 through the node 丨〇3. The node 1〇5 is connected to the input terminal of the inverter 1〇7, and the output of this inverter is connected to the node 1〇9 which supplies the output signal OUT. 1337002 CNTR2202 21757twf.doc/e, the holder circuit 111 is connected to the node 105. This keeper circuit U1 includes a first inverter 111A whose turn-in terminal is connected to the node 105 for receiving the k-number and whose output is connected to the input terminal of the first inverter 111B. The output of the first inverted state 111B is connected to the node 1〇5. Referring now to Figure 2, there is shown a timing diagram 200 of a dynamic circuit operation in which the CLK, DATA, HI, and OUT signals are plotted versus time. At time T0, when the CLK signal is low, N2 is held, φ and P1 are turned on, precharging the signal to a logic high to prepare the value of the DATA signal at the rising edge. During the half cycle of the CLK signal being low (ie, CLK is non-clock state), the OUT signal is also asserted low by the inverter. During the half cycle of CLK being low, the normal signal DATA is also low, as indicated by time τι, since the dynamic circuit 100 is typically configured in a cascade form as shown in Figure 1A, which is the OUT of the previous circuit. The signal is connected to the dATA signal of the latter circuit. Therefore, at time T1', since the DATA signal is at a logic low level, N1 is turned off. At the next time T2, the CLK signal is determined to be high (ie, clk is the "clock" state), turning N2 on and P1 is off. Since the DATA signal is at a low potential at the time T2, N1 is turned off, so that the HI signal is not driven by the input portion. However, during this period, the keeper circuit maintains the logic high level of the HI signal, and the inverter 107 maintains the out signal at a low level, thus preserving the state of the DATA sampled on the rising edge of CLK. However, if the DATA signal is driven to a logic high level during a half cycle in which the CLK signal is high, as shown by the time T3, then when N2 is turned on, c S > 11 1337002 i CNTR2202 21757twf.d〇c/e τ N1 Also, this causes the keeper circuit i]i to be overloaded to discharge the signal HI to a logic low. The response of the inverter 1〇7 is to drive the ου? signal to a high potential, thus changing the state of the output node 1〇9. Therefore, the output signal out no longer reflects the state of the data sampled at the rising edge of CLK.

In this regard, the inventors have noted that as understood by those skilled in the art, prior art dynamic circuit 100 shows that the set time requirement is (or in fact, less than G). This is because DATA is allowed to change from a logic low state to a logic high state at the rising edge of CLK, and the state of k output OUT is changed to reflect the changed data state. The CLK signal then goes low, and at time T4, the data 也 is also driven low, again pre-charging the m signal to a high potential. , t〇U Shi T signal is pulled low. At the next time Τ5, when DATA is low, the coffee signal is again determined to be high, so that N2 is turned on and turned off. Therefore, the HI signal is not discharged and is low. However, those skilled in the art will appreciate that the pulse is discharged at time and the QUT signal is flipped to a low potential. ,. The dynamic circuit, such as the dynamic circuit 100 shown in FIG. 1, is a logical bit other than the other t-way structure that implements the same logic evaluation function design (including the output of the static current channel (such as pre-charge i). : When the signal is low, the 'Hi signal is precharged to high power. The OUT signal is precharged to a low level. In fact, the 12 丄jj/υυζ CNTR2202 21757twf. d〇c/e is::=:( Such as: 1, N2) and evaluation logic unit evaluation logic unit (four) function) instead of dynamic circuit 1 () () in the user ί function, multi-input χ 〇 评估 评估 评估 评估 评估 评估 评估 评估 : : : Speed or related power restrictions have a negative impact. The _ ‘but—before” does not provide a staging mechanism for the input of the ... flash lock mechanism or 0UT signal. If the value of the above value is still high, the low-frequency signal is changed from low potential to high potential during the half-cycle period. =====: For the working area to provide stability for these devices == Workspace technology Involving the use of temporary work area techniques for existing dynamic circuits provides a pulsed period that is much shorter than a non-clock state period. For example, the pulse, the week makes the state -===, |(J 〇UT ^ the sampling state of the time T2 at which the potential is changed to the zeta potential. However, the above-mentioned working area makes the integrated circuit as a whole more complicated and/or generated. The pulsed clock signal is distributed. The two disadvantages of the present invention are therefore provided in the complex logic evaluation circuit, and the temporary storage mechanism is provided in the complex logic evaluation circuit, which adopts the dynamic circuit of the original county to improve the set time limit of the determination = display, greatly reducing the pair; It is required that the __ request is separated from the phase scale (S) 13 1337002 CNTR2202 21757twf.doc/e, so that the displayed clock output time is reduced compared to the present. The present invention will now be described with reference to Figs. 3-5. 3 is a schematic diagram of an inverting dynamic register 300 including a hold time reduction according to an embodiment of the present invention. The input portion of the dynamic logic register 3A includes a P channel device pl and an N channel device N2, which will be ^ The configuration is a pair of complementary evaluation devices, and an evaluation logic unit 3〇2, which is substantially opposite to the dynamic circuit 100. In one embodiment, the evaluation % logic unit 302 includes the N-channel device N2 shown in FIG. Other embodiments The other evaluation logic unit 302 structure includes p-channel and ^' or n-channel devices in a cascade and/or cascade configuration to implement a logic evaluation function such as a NAND function, an N〇R function, The combined NAND and NOR functions, including the multiple input priority order mux for more than one data input value logic, are not subject to this limitation. However, for clarity, the following description of the dynamic register 300 in accordance with the present invention is The operation includes the device N1 as an embodiment of the evaluation logic unit 302. The drain of N1 is connected to the precharge node 3〇7, and the source is connected to the drain of N2. The source of N2 is connected to the reference voltage, this reference The voltage is typically grounded. The pass node 301 provides the input clock signal CLK to the gates of ρι and N2, and the input to the non-inverting delay unit and the gate of the N-channel device N6. In one embodiment, the non-reverse The phase delay unit n or "buffer" 11 comprises two inverters connected in series. The input node signal DATA is supplied through the node 3〇3 to the gate of N1. The precharge node 3〇7 and the n-channel pass device N3 gate connection, and stacked The p-channel is connected to the gates of the N-channel devices P5 and N5. The pre-charge node 3〇7 is also connected to the first holding 13370702 CNTR2202 21757twf.doc/e circuit. The first-holder circuit includes a first inverter i4, The input terminal of the first-inverted $14 is connected to the node 3()7, with TOP, and the output of the first-inverter 14 is connected to the = terminal of the second inverter 13. The first inverter 13 The output is connected to node 3〇 7. The output of the delay early 11 is connected to node 304 to provide a signal KIU. Node 304 is also coupled to the source of path device N3 and the input terminal of the inverting delay unit. In an implementation, the inverse delay unit i2 includes a single reverse benefit. In other embodiments, the inverting delay unit includes an odd number of series inversions' to provide a delay associated with design requirements. Hereinafter, this inverted delay single Tt is referred to as an inverter 12. The output of the inverter 12 is connected to the gate of the p-channel device P3. The source of p3 is coupled to supply voltage VDD, and the drain of P3 is coupled to node 306 to provide signal KIL2. Node 3〇6 is also connected to the gate of N3 and the p-channel cutoff (km) device p4. The source of P4 is connected to the power supply voltage VDD, and the drain of P4 is connected to the source of P5. The drain of P5 constitutes a preiiminary output node 3〇8 to provide a signal Q. The primary output node 308 is coupled to the input of the second inverter 15 and to the second keeper circuit 313. The second keeper circuit 313 includes an inversion of 16, an input coupled to node 308 for receiving the signal q, and an output coupled to the input of the inverter 17. The output of inverter 17 is coupled to node 308. In addition, the drain of N5 is connected to node 3〇8. The output of the inverse 15 is coupled to the output node 315 to provide an output signal QB. The drain of N6 is connected to the source of N5, and the source of Νό is connected to the reference voltage. The output signal QB provides the inverted state of the input signal DATA sampled by the rising edge of CLK. 15 1337002 CNTR2202 21757twf.doc/e 1 ΛIn terms of operation 'with today's dynamic circuit described with reference to Figures 1 and 2', 〇 phase & dynamics provided by dynamic logic register 300 in accordance with the present invention • ❹米诺和Evaluate the inverted inversion function of the logic unit. The phase-shifted temporary storage 300 requires a set time for the input signal DATA to be approximately 〇, and does not require the pulsed clock signal clk. In addition, the hold time requirement for the inverse 1 'state temporary storage 1 300 is related to the shape of the sample DATA. The retention time requirements associated with the tribute, as discussed in more detail below, are advantageous in the case of a series of Domino circuit applications, especially if the aforementioned Domino stage provides a faster output than other CLK states.丨 status. According to Ben Maoming, in the first case where the sampled data is logic low, the requirement for the hold time can be optimized to optimize the aforementioned domino circuit to provide faster clock output time for the DATAk low potential to be converted to a high potential. . The inventors have noticed that the aforementioned circuit for providing an input signal is not necessarily a multi-circuit. As described above, the fP4 control allows the signal τ〇ρ$ to be transmitted through the output node 315. When the signal KIL2 goes high, the device P4 is turned off, thereby preventing the high potential from being transmitted to the primary output node 308 through p5 (if τ 〇 导). . According to the present invention, when CLK becomes a high potential, DATA is a low logic potential, and a path in which P4 is turned off after CLK becomes a high potential is accelerated. As mentioned above, this state is very useful in concatenating domino structures, because otherwise, as described with reference to Figures 1 and 2, if CLK becomes high and DATA returns to a high potential, the state of the output signal QB is output. Will change the g state. Also, as will be understood by those skilled in the art, a normal DATA evaluation is allowed for the initial take = 16 1337002 CNTR2202 21757twf.doc/e, which is a time requirement for the high logic potential DATA. '

In the first case where DATA is logic low during sampling, the signal TOP of node 3〇7 maintains precharge at logic high. Therefore, when clk becomes high, the path device N3 is turned on, and the logic bit of CLK passes through the delay unit II and passes through the turned-on path device to quickly turn off the Η. As will be understood by those skilled in the art, in the first case, the actual potential of the signal KIL2 is approximately VDD minus the critical voltage of Ν3 and this voltage is reduced by Ρ4, and the high potential signal is prevented from being transmitted through Ρ4 and Ρ5. To the node. Therefore, the time requirement in this case is mostly determined by the delay through the delay unit η. This is a useful case where it is desirable to have a reduced hold time requirement. In addition, during sampling, DATA rides a high level of the second level of the signal _P 307 of the node 307 "evaluate,, that is, when clk becomes high, TOP discharges to a logic low. When τ 〇 ρ discharge When the path device = wear stop 'forces the signal through the back leak 12 and the device ρ3; the path of sadness' is longer than the hold time of the first case. In addition, ^ even when the TOP part is discharged, To prevent the signal KIU from transmitting through the = two f Γ KIL1 through the device N3 to generate a signal KIL2 voltage approximating the TOT of the electric_de-threshold power, the sum of the delays of 12 and P3 is greater than the sum of the test to get the high eight 2 = Time 'to establish the correct potential on the primary output signal #uQ. The delay through 11 only needs to be long enough to cause the partial discharge of the signal TOP to force 1337002 CNTR2202 2l757twf.d〇c/e to be transmitted to node 308 to establish signal Q The logic is high, so the signal is held at a logic low.

However, when the T1 time TOP is discharged, the path device N3 is turned off. However, the state of CLK is not transmitted through the path of delay unit n, inverter 12, and p3, so P4 is turned off until time T3. Note that after N3 is turned off, the signal KIL1 of T2 becomes high at daytime, thus preventing the high logic potential from turning off P4 until the T3 time at which P3 is turned on. Accordingly, the evaluation window 〇1 according to the present invention is represented as EVAL·1 in Fig. 4, and the evaluation window 401 is determined via the sum of the delays of the delay unit n, the inverter 12, and the device p3 as described above. During daytime T4, CLK returns to a low potential, causing ρι to turn on, N2 and N6 to turn off, and precharge to a logic high. Therefore, N3 is turned on again, so that the low potential on KIL1 is transmitted to the node 3% through N3, so that when the low potential on clk is transmitted to the signal kiu through the delay unit ,, N is turned on at time HI. However, when D4 times T〇P becomes high, P5 stops I and isolates Q' and the keeper 313 maintains the state of node 308. Therefore, the state is the opposite state of Q. This causes:: 二崎八 is low potential' and CLK is high, and the bit remains =, : because the TOP 11 maintains a high potential on τορ. , ", is the same potential, and the signal KIU provides you with an acceleration cutoff path from Ν3 to r to 306.闵μ ',,, work to the point W T7 ^ ^ between the materials, the signal KIL1 by: ': 30 two and KIU becomes the potential. Passing from N3 to node 306 causes P4 to intercept 1337002 λ CNTR2202 21757twf.d〇c/e, while blocking the high-potential signal Q transmitted to node 308 via Μ so that DATA will return to a high potential. • At time T9 'DATA returns to high, TOP is discharged, and a N5 is turned off and P5 is turned on. However, at time T8, KIL2 uppers turns P4 off, and retainer 313 maintains a low potential on Q, that is, maintains a good potential on QB. Accordingly, the second evaluation window 402 according to the present invention is represented as EVAL 2 in Fig. 4, and as described above, the second evaluation window φ 402 is confirmed by the sum of the delays via the delay unit 11 and the path device N3. / The main idea is that the length of the second evaluation window 402 is a hold time requirement for a low potential on DATA. _ At time T10, CLK returns to a low potential, causing pi to turn on, N2 and N6 to turn off and again precharge T0P to a logic high. Therefore, N3 is turned on again, so that the low potential on KiL1 is transferred to node 3〇6 via N3, so that when the low potential on CLK is transmitted to signal KIL1 via delay unit n (at time T11), p4 is turned on again at time T12. And then P4 is turned off via N3 at time T12. However, when the time is 〇1 and TOP is high, Ρ5 is turned off and Ν6 is turned off, thereby isolating Q, and the holder 313 retains the state of the node 308 (logic high). Therefore, the state of QB is the opposite state of Q. At times T13 to T15, the operation of the inverting dynamic register 3A is substantially the same as the case of the above-mentioned discussion at times T1 to T3, and therefore is represented by an evaluation window 401 whose limits are limited to 13 to 15 . Referring now to Figure 5, there is shown a flow diagram 500 of a method of dynamic temporary storage of output signals in accordance with an embodiment of the present invention. u 20 1337002 CNTR2202 21757twf.doc/e Operation begins in step S502, in which the inverting dynamics are temporarily pre-charged in accordance with the present invention. That is, as in the embodiment discussed above with reference to Figs. 3 and 4, the first node is previously set when the clock signal is in the _th logic state. For example, in the previously described embodiment, when the cLK signal is low, the node 3〇7 providing the TOP signal is precharged to a high logic state. In step S503, when the current pulse signal is converted into the second logic state, the value of the logic function is obtained to control the logic state of the first node. Continuing with the previous example, when the % pulse "CLK" is asserted to a high potential, the evaluation logic unit evaluates the logic function based on one or more input data signals. When the tiger is discharged to a low potential state, the evaluation result of the logic function When the first state ° f TOP signal is discharged to the low potential state, the evaluation result of the logic function is the second state.

In step S504, the delay clock money CL = the muscle 2 is called the delay_day_number. When the estimation result is the first state, the truncation signal is accelerated, and the logic = the evaluation result is short in the second state. Enter the evaluation period or hold time of the > material that evaluates the logic early, between the working edges of the interrupt signal. It can be configured from the clock edge to the working edge of the wear-break signal KIL2 to ensure that the logic edge (4) is fine (four) correcting the day (four)' to provide in step S505, according to the logic state in the evaluation week, _ The logical state of the output node. The temporary register 300, if the phase dynamic logic 'holds the potential' during the evaluation period, outputs 21 1J37002 CNTR2202 21757twf.doc/e: No.: == If during the evaluation period, T0P is pulled to a low potential Turn the k唬Q latch to a high potential. In busy 506, the logical state of node 308 (e.g., Q signal) is terminated at the end of each evaluation period and the next evaluation. According to this

The logic state is determined at the end of the evaluation period, and the dimension of the dimension f is up to the beginning of the evaluation period. The integrity of the bribe output is not related to the fluctuation of the input data signal. Output Q in step V5, buffering and inverting the signal q of the output node 308 to provide a complementary output signal QB for driving the subsequent input of the red. The present invention provides configurable dynamics. The circuit is too ^ and the (four) guarantee (four) of the scratchpad. In addition, according to the ί=dynamic logic staging mechanism, its presentation-〇 set time requirement between time and time is a nominal (__clock output is the traditional temporary dynamic logic temporary storage machine with the logic estimator followed by Φ (10) delay anti- Phase; t fast. For the output TOP provided by the truncation mechanism described here, the Cong, = (four) interval is transmitted to allow the dynamic estimator to be greatly reduced by ^ Q. When the logical position # initial sampling - + shell The retention time requirement of the material input. The preferred embodiment of the version and 4=,, and ten thereof describes the present invention in detail, and other devices can be simply considered. For example, 'desired inversion dynamic temporary storage personnel type; To illustrate - 2 inventions use metal oxide semiconductor (M0S) type only, including complementary MOS devices, such as NM〇s and 22 丄州7002 CNTR2202 21757twf.doc/e PMOS 晶晶 n, also can be used It should be different or analogous. Technology and structure, such as bipolar devices, etc. • Finally, those skilled in the art will understand that they can easily use the disclosed concepts and specific embodiments as design or modify other structures. Foundation to implement this The same intentions of the invention are not deviated from the spirit and scope of the invention as defined in the claims of the invention. [FIG. 1 is a schematic diagram of a prior art dynamic circuit. FIG. 2 is a dynamic circuit of FIG. FIG. 3 is a timing diagram of an inverse dynamic register including a hold time reduction mechanism according to an embodiment of the invention. FIG. 4 is a timing diagram of the operation of the dynamic register of FIG. 3. FIG. Flowchart of the temporary storage output recording method of the present invention [Description of main component symbols] 100: Dynamic circuit β P Bu P3 : P channel device

Nl, Ν2, Ν6 : Ν channel device VDD: power supply voltage 10 卜1〇3,1〇5,1〇9,30卜3〇3,3〇4,3〇6,3〇7,3〇8, 315 : node CLK : input clock signal DATA : input data signal 107 , 16 , 17 : inverter 23 1337002 CNTR2202 21757twf.doc / e 111 : keeper circuit, 111A, 14 : first inverter 11 IB, 13, 15: Second inverter HI, TOP, Q, KIL1, KIL2: Signals OUT, QB: Output signal J 200, 400: Timing diagram 300: Inverting dynamic register 302: Evaluation logic unit Π, 12: Delay Unit N3: N-channel path device P5: stacked P-channel device N5: stacked N-channel device 311: first keeper circuit 313: second keeper circuit P4: P-channel intercept device 500: flowchart. ψ·. S502~S507: Step 24 of the embodiment of the present invention

Claims (1)

1337002 99-8-16 π years? Month/6曰 repair, patent application, a reverse-phase dynamic logic register, including · a pair of complementary devices, the threat-clock signal. An evaluation logic unit, connected to the sister: Series II =: The delay between the truncated signals includes a decrease in the hold time when the clock signal is maintained and the first state; and the 'heart' function is evaluated as the Gudi-door lock logic unit in response to the hash signal, the touch (four), and the iron The pre-state 'working edge for the butterfly signal' is the truncation; the number system output 3==evaluation week_between the state control according to the pre-charging node--Yushan,~' otherwise the output node is in a three-state state And the phase input has an input terminal connected to the output node and an inverse _ secret (four) register, and the P channel device has a _ receiving the clock signal and is connected to a power supply voltage a non-polar and a source between the pre-charging nodes; and an N-channel device having a gate receiving the clock signal and a source and a source connected to the reference voltage. Inverted dynamic logic described in the scope of patent application In the scratchpad, the evaluation logic unit includes the lion logic circuit. 25 ^^/002 ^^/002 99-8-16 (Year-by-month 丨 (? Japanese correction replacement page 4. If the patent application scope is the first item) The inverting dynamic logic register, wherein the delay logic unit comprises a buffer. 5. The inverting dynamic logic register according to claim 1, wherein the delay logic unit comprises a series connection 6. The inverting dynamic logic register of claim 1, wherein the delay logic unit comprises an inverter 'which is connected to the gate of the channel device'. The truncation signal is transmitted when the logic function is evaluated as the second state. The anti-phase dynamic logic register of claim 1, wherein the delay logic element comprises a - channel path device When the logic function is evaluated as the first state, the hold time is shortened. 8. The inverting dynamic logic register according to claim 1, wherein the latch logic unit comprises: a first channel a lifting device having the intercept signal a gate and a drain and a drain connected to the power supply voltage and m of the second 1> channel device, wherein the second P-channel device has a gate connected to the precharge node and a drain connected to the output node; And an N-channel pull-down device connected between the output node and the reference voltage, and controlled by the clock signal and the pre-charging node. 9. The inverse dynamic logic as described in claim 1 a register, a county circuit coupled to the precharge node, wherein the evaluation logic unit evaluates the logic function for the second state during the evaluation period, and at least one of the input data signals thereafter When the state is changed, the state of the pre-charge defect is maintained. 26 1337002 99-8-16 ί1年Μ ΜCorrect replacement page 1〇. —Dynamic register circuit, including ^-dynamic circuit' verification-clock signal is The low power office pre-charges a first node and is used to evaluate - the logic function is - the first state or a second state, and the recording signal (four) high power office, paving the state of the first node, - delay Logic circuit, Receiving the clock signal, and for providing a truncation signal, the truncated signal is a delayed clock signal, wherein the clock signal and the mine record delay include "hold off, and # the logic function evaluates to In the first state, the hold time is shortened; the shackle circuit is connected to the dynamic circuit and a delay inverter, and is used to start the pulse generation to become a high potential and to stop relying on the high potential energy The flattened weekly capture controls the state of the input & node according to the state of the n point, otherwise the output node is in a tristate state; and a keeper circuit that is coupled to the output node. 1丨_If the dynamic register circuit described in claim 10 of the patent circumference, the dynamic circuit includes: a p-channel device, which has no H-connection, and when the pulse signal is low, the first Node pre-charging; - logic circuit connected to the first node to evaluate the logic function; and _ N-pass slave 'Lin's circuit connection, when the clock signal becomes high, the logic The circuit evaluates the logic function to the second state. 12. The dynamic scratchpad circuit of claim 1, wherein the delay logic circuit comprises a series of inverter chains. The 暂 日 if if if 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 The channel ^, the pole connection, is used to transmit a break number when the logic function evaluates to the second state, wherein the number of the one or more inverters is an odd number. The dynamic register circuit of claim 12, wherein the delay logic circuit further comprises a channel path means for shortening the hold time when the logic function evaluates to the first state. 15. A method for dynamically storing an output signal 'includes: when a clock is listening to the n logic state, a first section is set in advance when the clock signal is converted into a second logic state, the dynamic evaluation logic: a first state or a second state to control a logic state of the first node, delay a clock signal 'and provide a job, the clock signal delayed by the letter; when the logic function evaluates to the first In a state, the mine signal is accelerated; and the first node is logically latched during an evaluation period starting from the time when the clock money is converted into the second logic state and the lower-corresponding transition a logic state of the output node; and a logical separation of the output node maintained between the evaluation cycles, wherein the latch comprises: a first channel riser 'having a gate ί receiving the cutoff signal - power supply type - source between the second set source 'U the second 1> channel device has a gate connected to the first node 28 mountain / 002 January 1 _ correction replacement page 99-8-16 Pole 'and the bungee connected to the output node And providing a plurality of channels Ν down means connected between the output node and a reference voltage, and controlled by the clock signal and the first node. 16. The method of claim 15, wherein setting the first node comprises precharging the first node to a high potential logic. ° Inverted 15 _ buffered and 18. As described in claim 15 of the patent application, the logic state of the output node between the estimated: includes: I:: in the second = condition 'and a keeper circuit Connect with the wheel dry point. 19. If the patent application scope is 棚15, the point is connected. The acceleration_money includes: an H clock circuit that shortens the delay time between the clock signal and the wear signal. 29