TWI300652B - Dynamic logic register - Google Patents

Description

13006 said _. ·

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▲ The present invention relates to a dynamic logic register and a scratchpad function&apos; and in particular to a dynamic logic register for the provision of temporary storage. [Prior Art] Ten general integrated circuits use a large number of registers, especially with a synchronous pipeline structure. The temporary logic element is the wire that allows the device to turn the wheel to the segment - so that the recording can be filled, and the circuit is pure. Such as in the county line (four) (four) (ρίρ_

M1C zero ocessor) clock system towel, its register is used for flash lock (four) - 仏 = line class _ number can be maintained in a clock cycle; 〇 c Cycle) 'by making the input circuit in the subsequent class can == The line class generates another new output signal while receiving the previously generated round-out signal. In the complex logic operation circuits used in the past, for example, multi-bit encoders, etc., are often accompanied by a register for maintaining self-transportation; circuit input or output. Generally, I wish that 'some temporary storage is related to the need to set up a coffee and maintain _, and 6 I30〇652 twfl.doc/006) f曰Revision replacement f 96-8^8 These two requirements will limit The arithmetic circuit in the pre-stage. In addition, the temporary decay of the register has the corresponding clock-output (clock_t〇_〇utput) relationship time = sex', which limits the operation circuit in the latter stage. Therefore, the temporary storage, and the rate are basically determined based on the data_output (data_tG_Qutput) °°, that is, the system is set to (four) plus the clock_output ^

The sum is to judge. If J uses a traditional $ at the back end of a logic operation circuit, it will cause a delay in the - pipeline system, and the result of the g product will be slowed down by the rate. The towel, the source of these delaying towels, comes from the set time requirement, which is to satisfy the logic operation and the road to ensure the stability of the temporary storage (4). For this reason, it is necessary to reduce these delays to add extra time, and at the same time increase the tube rate. In addition, it is necessary to optimize the characteristics of the pipeline system k / , in a wide range of operating environment towels can provide better performance. L invention content] The complementary pair, the Lei Zheng logic circuit, the dynamic calculation 11, the flash lock circuit and the complementary pair of one-dimensional operation elements correspond to the - clock signal and provide the π number and at = And - the operation node. The delay reverse logic receives the clock ^-Complete job'. The completion signal is one of the clock signals that is delayed. The wire is purely connected between the service node and the operation period, and during the operation period between the operation signal edge of the clock signal and the completion message-operation edge, according to at least one input resource 7 13_ Twfl.doc/006

8

The daily correction replaces the I 96-8-8 material signal to calculate the I logic function. The pre-charging node state locks the logic ethics, ^ f ^ is reduced and the state of the node is discharged by the pre-charge wheel during the operation period, and the shape is determined by the sorrow. In addition, the sacred damp charge charging section _ Prevent the input data signal from reaching the output node. The sustain circuit switch _ / / node it #- + is connected to the output point so that at the output = 7, the state of the output node, or the output point is not driven to a specific logic state. The channel ΐ ΐ η η η ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' Buffer/reverse has: one input to the output node and one of the input to the reverse output node. In an implementation configuration, the latch logic includes a P, a rain device (Pass Device), One and the second == components and one by the Ν_channel pull-down component (= 啦. Secret channel (four) components include: 1 pole = node - bungee and m = charge is point - secret - brother - Ρ _ The channel pull-up tree completes the signal, and the second drain of the pull-up control point is coupled to a source of the -source voltage. The second ρ channel includes a gate, which is reduced to Pulling up the control node, _ at the input t = 7 poles and _ at the source voltage - the source. The clamp ^ ^ is transferred between the precharge node and the operation node and corresponds to the completion 1 8 1300 end twfl.doc/006

No. 96-8-8, to clamp the pre-charging node to the computing node when the completion signal is in the low (l〇w) level state. A short stack of N-channel pull-down components is coupled between the output node and ground and is controlled by the clock signal and the pre-charge node. The clamping component can include an .-inverter having an output terminal and an interface connected to the completion signal: an input terminal; and an N-channel clamping component having: a surface interface connected to the pre-charging node One of the poles is coupled to one of the sources of the computing node, and a gate is extremely connected to the output of the reversed phase. The short stacked N_channel pull down component contains the first and second N_channel stacking trees. The first-N•channel stack=piece includes: a gate for receiving the clock signal, secret to the output: a point-bungee and a source. The second N_channel stacking component includes: an interpole coupled to the precharge node, a drain connected to a source of the -N_channel pull-down component, and a source coupled to the ground. A dynamic flash lock circuit in accordance with an embodiment of the present invention includes: a dynamic = two delay reverser '1 lock circuit and a turn circuit. The dynamic two-road pulse signal is pre-charged for the first node when the scale is low, and the second node is described when the signal is high-to-high, whereby the operation of the increment is used to control the state of the first node. This delay is reversed and provides a delayed reverse clock signal. The state of the challenge lock is determined by the first node in the calculation period: the distinct transit period starts from the clock signal and the same as the Lti. The pulse signal is delayed to the low level in the delay/ The node can be hung to isolate the output node. In the case, the _ circuit can include the first and the second N-pass 13006 said _ doc / 006 13006 said _ doc / 006 96-8-8 Repair: an inverter, a channel component and a stack component. The first N_pass component causes the third section to the node: when the reverse clock signal is high scale. Receiving the delayed reverse clock signal and the second channel; the second &amp; channel component in the delayed clock signal = the vertical node - node and the second node are secret. The ? channel element ^ the delay reverse The clock signal is low and the third node is pulled high. The stack 70 is low in the second node and the output node is pulled low when the node is high. The stack = 匕a two-channel component and a third, fourth N-channel component. The second P_channel component is the lower node when the third node is low_ a four-N-channel component between the output node and the ground: a coupling node = a dynamic temporary storage of the output according to the present invention when the pulse signal and the first node are both high-ordered The method of the tiger includes: At that time, the pulse is low-level on time to the first node to pre-charge, when the pulse signal is released to the high level on time (Rele Lang Yi: point ^ pull the second node 'at the time of the pulse - on time in the second : Calculate between the nodes - a kind of logic function to control the logic of the first node = sorrow' delay to reverse the clock signal to provide a delayed reverse clock signal = the beginning of the call to the high level and the end of the delay (four) During the operation period of the pulse level, the m point is used to control the output node of the gamma = the state of the output, and the logic state of the output node is maintained during the operation period, and the μ packet is clamped when the delayed reverse clock signal is in the low level state. Two nodes. u is the point to the 13006^ fl.doc/006 96-8-8 contains: pass-to-send: two-way to the output node. The method is packaged on time, the output node two: the second output The node is pulled low. The method can include: the output will be read as the pullup The control node isolation 'and the stacking method of coupling the first gate to the output node and the low level node may also include: inverting the delayed reverse clock signal ^private signal ', and at the time of the delay The pulse signal is a high level alignment drive-Ν channel element to clamp the first node to the second node. To make the above and other objects, features and advantages of the present invention more apparent, the preferred embodiments are described below, and DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The following description is provided in the context of a particular embodiment and its essentials, which can be made by those skilled in the art to practice the invention. Modifications to the preferred embodiment will be apparent to those skilled in the art, and the general principles discussed herein may be applied to other embodiments. Therefore, the present invention is not limited to the specific embodiment shown and described herein, but the maximum range consistent with the principles and novel features disclosed herein. u The invention of this case recognizes that the temporary storage rotation required by the logic circuit is the key factor of the logic circuit, and the optimization of the design of the positive body can be achieved by, for example, reducing the number of components. Equalize &amp; to increase the rate and reduce the area of the wafer consumed. Based on the above requirements 11.1300 end _ secret 8 〇 8 . Hand month correction replacement buy ' _____ 96-8-8

The inventor has developed a dynamic logic register that provides the input and temporary storage outputs required by the logic function, which is faster than the previous configuration and minimizes stacking— Channel elements, thereby increasing the degree and reducing the component and line layout area on the wafer, wherein the stack is used to isolate the sampling state of the output signal. Please refer to the figures f 1 to 4 for further explanation. When a pipeline architecture requires a large amount of data, the data can be transferred from the class to the temporary storage of another class to the dynamics provided in the embodiment of the present invention. The logical register can increase the capture rate and reduce the layout area of the wafer. 曰 Figure 1 is based on the related invention disclosed previously (US Application No. 10/73〇7〇3) A schematic diagram of a dynamic logic register (8) of a preferred embodiment. The input portion of the dynamic logic register includes a p_channel component 彳N channel component N2, which constitutes a complementary pair of operational components.

P1 is lightly connected to the source voltage VDD and its secret is connected to point 107 to provide a signal τ 〇 ρ. One is connected to the node 107^N2 less, m 0曰 狐心包路105. Between the bungee poles, the source of N2 is coupled to ground. The imaginary circuit 1〇5 can be designed, or it can include a more complicated signal such as the N-pass element to pull down, and the ship has a high-level punctuality to provide the T0P (DATA) to the mobile device. ^ Although although the figure shows only a single data signal, the operator will know the calculation of the domain 1G5 (four) line, but is familiar with this technique. Among them, the dynamic calculation of the H signal can be made in the course of the operation. Logical function performed or calculated by Jane ' 12 1300 end __6

96-8-8 The input clock signal CLK is supplied to the gate of pi and via the node ιοί, and then to the input of the delay reverse logic circuit 109 and the gate of the N-channel element N5, respectively. A Qualifying logic circuit 111 coupled to the delay reverse logic circuit 109 will be described in detail below.

The DATA input signal is provided to the input of the mobile bearer circuit 105 via node 1〇3. In addition, the node 1 〇 7 _ is connected to the gate of the &amp; pass ^ N ^ N6 ' N6 is connected to the source of N5, and the source of the can is coupled to the ground. The drain of N5 is coupled to the source of N-channel component N4, and the drain of N4 is coupled to a preliminary output node i2i. The output of the delay reverse logic circuit 109 is coupled to the node 117 to provide an operation completion signal EC, wherein the operation node 117 is coupled to the ? 2, N3 and Μ, the gate. The source of P2 is very fast. The node 1〇7 is connected to the source of the N-channel transfer element N3, and the drain of N3 is coupled to a pull-up control node 119 to provide a pull-up control signal pc.誃 Node Lightly connect to the drain of P2 and the gate of P3. Additional logic (^, such as Loglc) 115 is coupled between the sources of VDD and P3. The drain of p3 is coupled to the drain of N4 to provide a Q on the initial output node 121. A sustain circuit 125 is connected to the black junction m, the sustain circuit °i25u includes a first inverter 125A, the wheel end is coupled to the node i2i to receive the Q signal and the output terminal is coupled to the second reverse The output terminal of the second inverter 125B is coupled to the node i2i. In the embodiment, the sustain circuit 125 is a weaker dimension which needs to be performed by stacking of the pull-up element P3 or the pull-down element N4_N6. Strong 13 130065?^,oc/006 96. R q

1 year 13⁄4 correction replaces I 96-8-8 (Over-powered). The output is connected to the input of the / buffer 123. The output of the reverse/buffer 123 produces a Reverse output signal QB. "Buffering" is advantageous for driving the input of the next logic or latch circuit, especially where the stack of elements P3 and N4-N6 typically displays a tristate to the node 121 and the inverter 125B is relatively In the case of a weaker component. The inverter/buffer 123 can be replaced by a non-inverting buffer to prevent logic inversion. However, a non-inverting buffer is typically implemented as a back-to-back reflector, which may increase the undesirable delay and increase the clock-to-output delay time. As described in the previously disclosed U.S. Application Serial No. 10/730,703, the interconnected components P2, N3, P3, N4 and the additional logic circuit 115 form a latching mechanism for the top signal whose state is rising at CLK. The short operation period between the edge and the falling edge of the EC signal is determined. The Ec signal is a delay reverse signal of CLK, which is referred to herein as a reverse delay clock § il. The TOP state during the transfer is transmitted to the PC signal via the transfer element N3. If the dynamic logic signal pulls τ 〇 ρ low, then the TOP turns off the Ν 6 and the PC turns Ρ 3 on. If the additional logic circuit 115 has supplied VDD to the source of p3 during the operation, a logic "high" state can be provided to the output signal q via P3. If the additional logic circuit 115 is turned off during this period, the state of Q remains in the state previously established by the sustain circuit 125 even if P3 is turned on. After the delay period, the EC proceeds to a low level, causing N3 and N4 to be turned off, and p2 to be turned on, 14 1300652

15436 twfl.doc/006 96-8-8 This pulls the PC high, thus causing the weaker sustain circuit 125 to 2 and the turn Q to be tri-stated. The rest of the clock cycle remains in its recurring time period. When the EC signal passes through a knot to a low level, it represents that the use has been completed, and = W QB is in the form of a half cycle. To the output "QB's sadness. During this half-week period, the low level is on time, Ρ3 will also protect the rabbit against the At field / the team is still 掊 掊 sign n &amp; π * temple is closed, and the output Q will be guaranteed In the condition that component P1 is turned on and Ν2 _ is precharged to a logic high state. After the delay 'when the EC proceeds to a high level, the component (10) is turned on, allowing the doctor (which is pulled high via P1) Maintaining a high level on the PG, thus keeping P3 off. The delay reverse logic circuit 1〇9 can be implemented in different ways, for example, by coupling one or more inverters in series. The limiting logic circuit 111 is used in combination with the delay inversion logic circuit 109 to effectively disable the EC signal from becoming a high "level" state when the CLK is at a high level, thereby preventing the obtained logic function TOP from being transmitted to the node via N3. Output QB. Functionally, this allows the designer to maintain the previous state of the QB during subsequent clock cycles. The dynamic logic register 1 provides a combination of the rate and the nose of a dynamic circuit. In addition to effectively reducing the hold time of the input data, the scratchpad can have an output retention property. The 15 c/006 month correction correction tribute ': 96-8-8 dynamic logic register 1 〇〇 shows a zero set time, short hold time and very minute clock-output time, motivating Its speed - much faster than a combination of latches placed before and after the logic calculator. After the delayed reverse CLK is combined with the above-described latching mechanism, the output of the dynamic calculator T〇p can be allowed to be transmitted to the output Q during a very short interval. After this operation period, when CLK is in a high level state during the remaining half cycle, the stacks P3, N4, N5, and N6 will operate together, and in the subsequent half cycle, when the CLK is low level and In the high level state, a three-state condition is maintained on the output node 121, whereby the sustain circuit 125 maintains its state in a pre-occurring state during the operation period. The dynamic logic register 100 disclosed in the present invention provides input latching and output temporary storage functions of complex logic operation functions, which can eliminate the set time requirement commonly seen in the LATCH-LOGIC-LATCH combination. , resulting in shorter data-output characteristics. In a wide range of operating environments, for example, in an environment characterized by low temperature, low voltage, and a process that produces fast P_channel components and low speed N-channel components, it is necessary to have a dynamic logic register. Features are optimized to provide superior performance. In various simulations, the storage node is isolated from the stack containing three N-channel components N4-N6, which presents an opportunity to improve the rate of the dynamic logic register. Those skilled in the art will appreciate that the reduction in the number of elements in the N_ or Bu heap can result in improved speed and further savings in material production. For example, 'It should be known that when it is carried out by 2-component stacking to 3 I3〇〇6^ •d〇c/〇〇6 I3〇〇6^ •d〇c/〇〇6 96-8-8 Correction replacement 兀: Shih Fufeng 'If you want to maintain one and two in the 3-component stack: the same pull strength in the stack of parts' then not only need another electric L cow = body: each must be 2 The visibility of the cattle in the component stack is 1.5 times larger. Therefore, the area of the wafer circuit is provided to provide the same pull-down strength. In the meantime, the dynamics of the preferred embodiment of the present invention, the same as the dynamic register (4), are denoted by the same reference symbols. The stack of three ν_components Ν4_Ν6 is reduced to a stack of two Ν_channel components Ν5 and Ν6, where Ν4 has been deleted, and the enthalpy of Ν5 is directly connected to the initial output node 121. The node ι7 carrying the EC signal is supplied to the input of the inverter U1, which provides an EC reverse signal (referred to as an ECB signal) at its output on the node. Since the operation completion signal EC is a delayed reverse signal of CLK, the ECB signal is a valid CLK delay signal, which is called a delayed clock signal. The node 201 is coupled to the gate of a new N-channel component N7, the N7 of which is depleted to the node 107 (the τ〇ρ signal) and its source is lightly connected to the drain of N2. The drain of N2 forms a node 203 that can issue an operational signal. In the same manner as the dynamic logic register 100, the N2 pole, or the EV signal, will be pulled down to a low level when CLK is determined to be in a high level state for the tracking circuit 105 to perform. Yun Hao. When the EC signal becomes a low level, it is necessary to isolate the output node length: for Q §fl number' and this isolation function is achieved by the previous dynamic logic temporary buffering 100 components P3 and N4. The isolated output signal Q is considered to be the interference that may be caused by the DATA input signal in the circuit of 96-8-8 in the circuit of the El-correction page 96-8-8. The time when the human domain needs to be stable is called "," (holc^,. After the retention time expires, the DATA input has not been kept private. In the dynamic logic circuit 200, deleting N4 will make N-channel 70 pieces. The stack is dropped from 3 components to 2 components, but the channel component N5 cannot be provided. The path isolation machine provided by port N6

Structure,! Γ嘹! 1 out point 121 cannot be isolated from the ground. Therefore, if the TOP gas is estimated to be in the record, then DATA will be undated when ec becomes a low level (and N5 * CLK signal is turned on) may be made, T ^ becomes a level state, ^^'s conduction will be pulled Low to lose

And the inverter U1 and the N-channel component N7 are combined to form a two-f clamp mechanism, and the node ^lamP) is leveled with the node 203 when the EC signal is at a low level, so that the T0P signal is one. ;,, return level (although DATA has fluctuations), until CLK is followed by the box: coveted level so that the TOO signal is only gamma t in the next calculation cycle. The improved dynamic logic register 200 can confirm that the 1C tiger has remained low since the EC was lowered to a low level until the person became a margin. Therefore, tEc turns to a low level,

T0P EV ί yells into the lower position for "external TW signal into -V w ^ 兀 兀 N N N N N N N N N N

The type can deliberately cause the T〇P S EC to be a low-level on-time discharge, so that the output signal Q can be isolated during the remaining half cycles of the CLK 18 96-8-8 13006^2^^/006 &quot;5 signal. Figure 3 is a timing diagram showing the operation of the dynamic logic register 200 in which the CLK, EC, ECB, DATA, TOP, EV, PC, Q, and QB signals are plotted against the time axis. At T0, the CLK signal is low and the TOP signal is precharged to a "high" logic level. The EC signal is initially at a high level, and P2 is turned off and N3 is turned on. Therefore, the PC signal is initially pulled to a high level by the TOP signal via N3. The ECB signal is the reverse state of the EC signal, so it is initially at a low level and N7 is turned off. P3 and N5 are turned off to provide a three-state condition to the Q signal, i.e., the sustain circuit 125 maintains the Q signal in the previous state. In the case described, the q signal is initially in a logic "high" state at T0, while the qB signal is at a low level, and the DATA 4 is at a south level. In the particular configuration shown, the dynamic calculation circuit 105 effectively couples the nodes 107 and 203 when the DATA signal is at a high level. Therefore, even if CLK is at the low level and N2 is turned off, the TOP signal will initially pull the EV signal high through the dynamic calculation circuit 1〇5. The operation period begins at each rising edge of the CLK signal and ends at the falling edge of the delayed reverse clock signal EC. During the operation: The time period is defined by the delay reverse logic circuit 1〇9, the delay amount, . The CLK signal rises at the next time point T1, causing ρι to turn off and turn N2 and N5 on for initialization - as indicated by the first operation indicated by reference numeral 3〇1. The EV signal is pulled low when N2 is turned on. The state of the τ 〇 ρ signal during the operation? ' depends on the difference between the dynamic calculation circuit 105 and the hidden signal. In the embodiment of the dynamic computing circuit 1〇5 shown, the 13 13003⁄4 3twfl.doc/006 date correction corrects the data signal at a high level at time T1, causing the dynamic calculation circuit 1〇5 to operate during the operation 301. The 胄τορ signal is pulled low, so that '* Ν6 is off. Since the EC signal remains high at 3〇1 during the operation, f therefore the state of T〇P is transmitted to the PC signal via N3, which also causes the pc• signal to become a low level and P3 to be turned on. Assuming that the additional logic circuit (1) supplies VDD to the source of P3 during the operation, the Q signal will be pulled high (or still remain high) and the QB signal will be pulled low (or still remain low). At T2, since the delay period of the delay reverse logic circuit 1〇9 has expired, the EC signal becomes a low level, N3 is turned off, p2 is turned on, and the operation period 301 is ended. The ECB signal becomes the high level commander N7 is turned on and the node 1〇7 is clamped to the node 203, so that the EV pulls the TOP signal low when the N2 is turned on. The PC signal is pulled high by VDD via P2, causing P3 to turn off. Since CLK is at a high level, N5 remains on. When DATA is kept high, the T0P signal is at a low level and the N6 is turned off. T3 at CLK at a high level

• During the half cycle, the DATA signal becomes a low level. Although N2 is still bran, it depends on the special composition of the dynamic calculation circuit 1〇5, so that the state of the signal will not be determined, and the fluctuation of the DATA signal may unexpectedly cause the TOP §fl to become a standard. Although the inverter 拉ι pulls the ECB high and turns N7 on during the remaining period, however, the top of the top remains low and N6 is turned off, leaving Q still isolated. In this way, fluctuations in the D A T A signal will not pose a threat and cause the Q signal to be pulled low. The sustain circuit 125 will cause Q 20 !3〇〇6^άο, c/006 in the remaining period in which CLK is high.

96-8-8: No.: Hold the $ quasi, and the reverser 123 will keep the (9) signal in the logic edge. In the T4, the falling edge of the CLK signal will be turned back on again by ^ and Pl. The state, then the τορ signal is again passed through the VDn + 1 of P1, and the number becomes the low level when Τ 4 becomes 5 = becomes the high level. In the CLK, the turn-on N6L is turned off, so that even if the TOP is pulled high, CLK is at time Τ4; then:f2 remains in isolation. Since the ancient ^, and the low-level punctual N2 closed, and because the team 8 is still TOP Lagu ^ Tong 'T 〇 P is no longer pulled by Ev 'relatively' EV H signal at time T5 becomes high punctuality, The high level of N3, OFF, and W〇P is transmitted again through the transmission element N3. At this time, the PC signal remains at a high level and P3 is turned off. ; TA 疋 low level and N2 and N7 are off, so at time T5 ^ CLK, the remaining period of the low level, as indicated by the number 3 〇 5, the state is undecided. Although the EV maintains a high level state because it has been previously driven to a high level, and may be driven to a high level due to high data interference, the state of the EV is still illogical during this time. The operation is basically the same when the CLK signal starts at a rising edge at time T6. However, in this case, the DATA 汛唬 (which is a high level at a rising edge before the CLK signal) is a low level and is about to become a high level approximately at the same time as the CLK signal at time T6. When the EC signal becomes low, in the second operation period from time T6 to the next time T7, since the DATA signal 21 13006 says that the MTWTE~~~ Niuyue Day correction replacement page 96-8-8 is a high level, The DATA signal can be correctly calculated by the dynamic calculation circuit 105 in a sufficient time operation, so that the Q and QB signals can be determined to be in the correct state. In this way, those skilled in the art can know that the set time can be successfully calculated because of the logic function even if the data signal transition time is almost the same as the initial operation time of CLK. Valid value is zero. During the third operation between the rising edge time T8 of the CLK signal and the next falling edge time T9 of the EC signal, as shown by reference numeral 3, the operation is similar. However, in this case, the DATA signal is set to a low logic level, causing the dynamic calculation circuit 105 to fail to perform the operation, and the TOP signal is kept at a high level to maintain the on state. Since the Ec nickname remains at a high level, N3 is turned on and the TOP high level state is transmitted to the PC signal and P3 is turned off. The Clk signal turns on N5, and since the TOP remains at a high level, the Q signal is discharged to a low logic level via a short stack formed by pull-down elements N5 and N6 at time T8, and the QB signal is also approximately At time T8, the inverter 123 is set to a high level. When the EC signal becomes low at time Τ9 and the operation period 303 ends, the pC signal is pulled (or maintained at a high level) by VDD via Ρ2, causing p3 to be turned off. Although the DATA signal can still maintain a high level when the DATA is kept low at time T9, the Τ0 signal is still clamped to the low level by the EV via Ν7, because the ECB signal becomes a high level. Caused. Therefore, when the operation period 303 expires, the Ρ3 spear Ν6 component again provides a three-state condition to the Q signal. Similar to the manner previously described, by the maintenance circuit 125 22 13〇〇6 total l.doc/006

96-8-8 During the remaining period of the period, in the Q mode, the Q and QB signals will still be during the CLK period after the expiration of the operation period: the EC signal passes through the component P2. P3, N3, n; the lion is clamped to the logic circuit and becomes a low-level punctuality. The temporary storage function is completed when the period of each calculation period expires ^

The level (4) is turned off and P2 is turned on: P3 is turned off, and the medical signal is pulled low by N7 via the ECB. Since the H CLK signal is the first first half of the clock cycle in which the clamp is on time, the q signal is isolated from the pull-up element N5 and the formed stack by the pull-up element P3. When the CLK signal becomes low to start the second half of the clock cycle, N5 will be turned off and the Q signal will remain when the EC signal remains low and P3 remains off (it is still pulled up) The pull element remains in the state of 耆 isolation. At the same time, the conduction of P1 and N2

The shutdown will cause the top signal to be pre-charged to a high level. When the Ec signal becomes high, N3 turns on, allowing the high level of the TOP signal to be transmitted to the PC signal', thus keeping P3 off. The state of the Q and QB signals is maintained by the sustain circuit 12 5 regardless of the change of the input data signal from the expiration of each run period to the start of the next operation period. The function of the additional logic 115 circuit is to ignore or prevent a high level of logic output on the Q signal tiger. The limiting logic circuit 111 is coupled to the delay inversion logic circuit 109 to effectively disable the EC signal from becoming high when the CLK signal becomes high 23 130061 doc/006 % 8 thousand days to correct the replacement page 96-8-8 level. This prevents the TOP signal representing the arithmetic logic function from being transmitted to the output terminal QB via N3. Such a function allows a designer to maintain the previous state of the Q and QB signals during subsequent clock cycles as necessary. Figure 4 is a flow chart of a method of dynamically suspending an output signal in accordance with a preferred embodiment of the present invention. The operation begins in step 4〇1, and when the clock signal is low, the first node is pre-charged. In step 4〇3, the day π pulse signal is shifted to a high level to open a logic function π, for example, the sorrow circuit 105 is based on one or more inputs when the clock signal is determined to be a high level. The data signal is used to perform a logic function operation, and a node is released and the second node is pulled low to control the logical sorrow of the lang2. . In step 405, the clock signal is delayed and inverted to provide a delayed reverse clock signal. For example, the delay logic circuit 109 delays the CLK signal to provide an EC signal. The period of the chirp delay can be set to provide the minimum delay required to ensure that the logic function is counted. In a synchronous pipeline structure, such as a s-line microprocessor, § or the like, the delay of the class can vary depending on each logical function. Alternatively, the minimum time delay can be used to calculate the most common ambiguity required in each class. During the operation period established by the delay, J is at the transition point of the operation of the clock signal (for example, CLK above, pi, and the lower-transfer point of the reverse pulse signal with respect to the delay (example) tL next falling edge). In Y step 407, the logical state of the output node is based on the operation 24 1300652 1 j43otwfl .doc/00&lt;

The year 1 R correction is controlled by replacing the logic state of the first node determined during the J 96-8-8 calculation period. Please refer to the dynamic logic register 1〇〇. If the TOP keeps the status of the ^ and · during the operation, the Q signal will be latched to the low level, but if the T0P is in the low level, the Q signal will be The latch will be latched to a high level - in step 409, the logic of the output node (e.g., Q signal) will be maintained between the expiration of the computation period and the beginning of the next computation period. Included during operation or at least between the next time the CLK signal goes low, the first node to the second node isolates the output node from the first node: in the illustrated embodiment, reversed by U1 The resulting Ec signal will provide a delayed clock signal ECB, which will cause ** to be pulled low after the end of the operation period until CLK becomes low level again next time. ϋ 'Read the heap 4 component N6 off _ _ the output node. A: Kind: In f4, 'once the logic state is determined after the expiration of each operation period', the output state will be maintained until the next-operation period to ensure the integrity of the output number, regardless of the input data signal change. Whether or not. In the (four) 411 towel, buffer and reverse the output node to rotate the subsequent input to the end. θ A dynamic logic register according to a preferred embodiment of the present invention, which provides a combination of speed and operation of a dynamic circuit, which not only effectively reduces the maintenance time of the wheel data, but also enables the register to have Output capital (four) to hide, the department displays - the material set time, a very!!, hold time and a very short clock - output time, so that the ^ and the car 乂 another ~ kind of before and after the logic calculator The group with the flash lock is very sad. A CLK delay reverse signal (eg, EC signal) is at 25 1300 _. — ία &quot;—*—»— 丨Revised replacement page 丨96-8-8 运和: Two mechanisms can be combined to provide a short operation period during which this dynamic calculator can be allowed to rotate (for example , τ〇ρ

Starting with Sim, the node (for example, 'q signal). In the operation ^ 乂 black, stacking components (for example, p3, n5, n6) in the clk «疋冋日日代半半巾 towel CLK signal is the low and the right half of the half cycle: provide to the initial output node. ―Form a way to keep the TOP low imitation, splicing the citrus smuggling in each A wind, and the Fentian low is good for the output node and the shame channel component is deleted in the heap configuration so that Make more of the best in the two worlds: i)) I hold) Μ Μ Μ 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道 通道Area. Temporary storage = - provided by the preferred embodiment - dynamic logic provides complex round-robin = lock and output temporary storage functions for complex logic calculation functions. In addition, since the present invention can be disabled in L0GIC-LATCH configuration The required set time, so the time characteristic is significantly reduced. Dynamic logic register balance::: even complex logic operation function provides flash lock input: can be faster than the current configuration. When the temporary storage of the large-scale temporary-passage-level-passage-level pipeline architecture, the operation rate of the overall component can be greatly increased. Although the present invention is described in detail with the preferred embodiment.逑, ~ his preferred embodiments and variations are also possible and predictable. Example 26 13003⁄43⁄4 itwfl .doc/006

96-8-8 Roads can be designed to be simple or very complex. The pain-relieving circuit and the additional logic circuit may also be omitted or implemented in any suitable manner known to those skilled in the art. [Although the embodiment of the present invention provides a metal oxide semiconductor (M0S) type device] It includes complementary metal oxide semiconductors 兀 = 'such as Li Wei S and PM0S transistors, but it can still use the class

It is implemented in a similar or analogous form and architecture, such as bipolar elements or similar components. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of a dynamic logic register in accordance with a preferred embodiment of the related invention disclosed previously. Figure 2 is a schematic illustration of a dynamic logic temporary storage in accordance with a preferred embodiment of the present invention, including a clamping mechanism for isolating an output node. Figure 3 shows the operational timing of the dynamic logic register in Figure 2.

Figure 4 is a flow chart showing a method of dynamic temporary storage round-off signal according to a preferred embodiment of the present invention. [Main component symbol description] 100 dynamic logic register 101, 103 node 105 dynamic calculator 107 to logic circuit pre-charge node 109 delay inverse 111 limit logic circuit 27 Ι3〇〇6^.άοε/006 H-day correction replacement page丨96-8-8 _________T-f -- , , J 115 Extra-added logic circuit 117 Operation node 119 Pull-up control node 121 Initial output node 123 Inverter/buffer 125 Maintenance circuit 125A First inverter 125B Second reversal 200 dynamic logic circuit 201, 203 node 301, 302, 303 during operation 305 undetermined state 28

Claims (1)

1300 tilt - 6 96-8-8 ten 'patent scope: dynamic logic register, which includes: π component complementary pair, corresponding to a clock signal and provides a pre-charge node and an operation node; delay reverse The logic circuit is configured to receive the clock signal and output the signal, and the pulse is delayed and reversed to form a completion signal; the dynamic meter # is connected between the precharge node and the operation node j 'In the operation edge between the clock signal and the completion signal, and during the operation between the edges, a logic function is calculated according to at least the input data signal; ^, an attached circuit, corresponding to The state of the clock signal, the completion signal, and the state of the pre-charging node are determined by the state of the pre-charging node during the operation period by the state of the pre-charging node, and the pre-charging node is prevented from The fluctuation of the input data signal is transmitted to the mountain out point; and a maintenance circuit is coupled to the output node; wherein the latch logic circuit includes ·· ms 乂 channel transmission 70 pieces 'with ·· for receiving The end One of the signals is coupled to a drain of the pull-up control node and a source coupled to the pre-charge point; a first P-channel pull-up component having a receive signal for receiving the completion signal a gate coupled to a drain of the pull-up control node and coupled to a source 29 !3〇〇6^^fl.doc/006 !3〇〇6^ ^fl.doc/006 96-8 -8 Ιί % corrects a source that replaces the i-pole voltage; the point ^ puller' has a coupling to the pull-up control section = 2: _ at the wheel-out node - and the pole and the handle are connected to the source The clamp 4 component smashes the signal at the pre-charge node and the operation node to clamp the pre-charge point to the operation node when the completion signal is at a low level; and the ground stack Γ-channel pull-down element Lightly connected between the output node and the interface h' and controlled by the clock signal and the Wei charging node. 2. The dynamic logic register as described in the scope of the patent scope is set forth in the middle. The complementary pair of components includes: /, P-channel 70 pieces, having: one for receiving one of the clock signals, and the bridging and coupling at the charging node a source; and an N-channel 7 element having: a gate for receiving the clock signal is lightly connected to the node of the different node - the drain and the g are connected to one source of the ground. The dynamic logic register of claim i, wherein the clamping component comprises: /' an inverter having an input end and an output end coupled to the completion signal; And an N-channel clamping component, comprising: a pole coupled to the pre-charging node, the handle being connected to the operating node, to listen to the 'gate of the output of the inverter 4. The dynamic logic register as described in claim 1 of the patent scope, the 30 13006 said __% Wfiil 96-8-8, the short stacked N-channel pull-down element comprises: : a gate for receiving the clock signal, _ to the output node - the drain, the - source; and a second channel stacking component, including the gate of the coupling The source of the first-channel channel pull-down component; the 3-pole and a source connected to the ground. 5. As in the dynamic logic register of claim i, the basin further includes an -plus logic circuit between the Wei pole voltage and the 2 P-channel pull-up element to prevent the output. The slave of the node is separated from 6. If you apply for the patent scope! The item includes: an output buffer/inverter having: an input coupled to the "node" and an output coupled to an inverted output node., 7 - Dynamic latching The circuit includes: · the circuit 'in-the clock signal is a low-level on-time-to-node 仃" power, and pulls a second node when the clock signal turns to a high level: in order to calculate f - a logic function to control The first node is configured to receive the clock signal and provide a reverse to be coupled to the dynamic circuit and the delay inverter at 1, ending with a delay of “z====== In the inverse =, the state is from the state of the first node; system: and the point to isolate the output node; and the brother-maintaining circuit, to her to the output node; 31 1300 from Ldoc/d Κ.Τ· 3——— Year, Month, Day Correction Replacement Page 97-05-13 The question lock circuit includes: a first Ν-channel component for consuming a third node to the reverse delay clock signal when the pulse signal is high The first node; an inverter for receiving the reverse delay clock signal and providing a delay Signal; a second Ν-channel component, wherein the delayed pulse signal is a high level keeper, and the remote node is connected to the second node; the channel component is used for the reverse delay clock The signal is low when the third node is pulled high; and a bunch of 7L pieces is tied to the input (four) point, and the output node is high when the third node is low and during the operation, if the A node is high and the output node is pulled low. The secret path of the seventh item of the electric system, wherein the one is: a channel element for precharging the node when the clock signal is low; Λ a logic circuit coupled to the first And the second to calculate the logic function; 卩", between: the N_it channel component, which is connected to the second node, to cause the logic circuit to calculate the logic function when the ring is turned to a high level. For example, the dynamic lock circuit of the seventh item of the patent scope includes: , r 琢 a second P-channel component, which is pulled high at the third wheel take-out node; and the node is at a low level 32 years month g correction replacement 寅· I3006^, doc/O06 Section 11 of the dynamic temporary storage output signal between the third and fourth fourth channel components is coupled in series between the read output node and the ground for the clock signal and the first = Both are high and the output node is pulled low on time. The anvil 10. The dynamic latch circuit of claim 7 further includes an additional logic circuit, _ connected to the lock circuit to prevent the predetermined logic state. "," occupies a dynamic temporary output signal method, including ·· = a clock signal is low-level on time, pre-charging a first node; when the clock signal becomes high, releasing the first point And pulling down a second node; the military 瞀 is connected to the first node and the second node H logic function performs π, the logic function controls the logic state of the A point when the clock signal is high level; And reversing the clock signal to provide a delayed reverse clock signal; at the beginning of the time when the pulse signal is turned to a high level and ending at the delay time, the pulse signal is converted to a low level operation period, Controlling, by the first node, a logic state of an output node; and 'maintaining a logic state of the output node between each of the different periods of time, including: the reverse clock signal is a low level, clamping the first; Point to the brother Erlang point. 12·If you apply for the patent scope, the law 'is further included·· buffering and reversing the output node. 13.If the dynamic temporary storage output signal of item U of the patent scope is 33, Twfl.d〇c/〇〇6 - The well r maintains the round-out node light-holding-maintaining the lightning-weaving&amp;, the transition includes: the material path to the round-out node. The step includes ·· 剌; the output is the logical state of the point of the transfer of the first node The logic is as follows: the pull-up control node 曰 control node; quasi; and ", 疋 low-level quasi-訏, pull the bit of the round-out node = Hi point 疋 horse position on time, pull down the level of the output node. Method, the LH range 帛 14 items of the dynamic temporary storage output signal, the second step of maintaining the logic state of the output node includes: deviating from the round-out node and the pull-up control node; and clamping the first node For the low level state, the components are stacked with __ between the output ray point and a low level node. The method of the dynamic temporary storage output signal of claim 15 wherein the clamping of the first node to the low level comprises: reversing the delayed reverse clock signal to provide a delayed clock signal; When the delayed pulse signal is at a high level, an N-channel component is driven to clamp the first node to the second node. The latching logic enables the state of an output node to be determined by the state of the pre-charged node during the evaluation period and otherwise clamps 34 I3〇〇6^ doc/006 96-8-8 of the clock and complete signals. The pre-charged node to prevent perturbations of the data signal from propagating to the output node. VII. Designated representative map: (1) The representative representative of the case is: Figure (2). (2) A brief description of the component symbols of this representative diagram: 100 Dynamic Logic Register 101 ^ 103 107 117 105 109 111 115 119 121 123 125 125A 125B Precharge node operation node dynamic calculator delay reverse logic circuit limit logic circuit additional logic circuit pull-up control node initial output node inverter/buffer sustain circuit first reverse Second reverser 4 13 ___ 96-8-8 200 Dynamic Logic Circuit 201, 203 Node 8. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention: