CN1731679A - Dynamic logic register and signal output method thereof - Google Patents
Dynamic logic register and signal output method thereof Download PDFInfo
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- CN1731679A CN1731679A CN 200510090699 CN200510090699A CN1731679A CN 1731679 A CN1731679 A CN 1731679A CN 200510090699 CN200510090699 CN 200510090699 CN 200510090699 A CN200510090699 A CN 200510090699A CN 1731679 A CN1731679 A CN 1731679A
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Abstract
A dynamic logic register including a complementary pair of evaluation devices, delayed inversion logic, a dynamic evaluator, latching logic, and a keeper circuit coupled to the output. The evaluation devices are responsive to a clock signal and provide a pre-charged node and an evaluation node. The delayed inversion logic outputs a complete signal that is a delayed and inverted version of the clock signal. The dynamic evaluator, coupled between the pre-charged and evaluation nodes, evaluates a logic function based on a data signal during an evaluation period between operative edges of the clock and complete signals. The latching logic enables the state of an output node to be determined by the state of the pre-charged node during the evaluation period and otherwise clamps the pre-charged node to prevent perturbations of the data signal from propagating to the output node.
Description
Technical field
The invention relates to a kind of dynamic logic buffer and buffer function, and particularly relevant for a kind of dynamic logic buffer that temporary output is provided in response to logic computing function.
Background technology
The present invention is to advocate as rights and interests of the present invention in the full content and the purpose of the temporary transient application case of application in the U.S. on August 27th, 2003 number 60/498187.
Simultaneously, the present invention be with following U.S. partly continuously case try jointly, this partial continuous case and the present invention have a common assignee and at least one common inventor, and are used as the list of references of the application's case in conjunction with its whole content and purpose.
| U. S. application case number | The U. S. application date | Patent name |
| 10/730703 | ?12/5/2003 | Dynamic logic buffer (DYNAMIC LOGIC REGISTER) |
General integrated circuit all uses a large amount of buffers, especially has the integrated circuit of lock-in tube line structure.The buffer logic element is to be used for allowing the output of device and circuit keep a period of time, so that these outputs can be received by other device and circuit.As in a kind of microprocessor (Pipeline Microprocessor) clock pulse system of pipeline, its buffer is used for the output signal of the given pipeline class of breech lock (latch) and can maintains in the clock pulse cycle period (Clock Cycle), makes the output signal that produced before the input circuit of follow-up class can receive when this given pipeline class produces another new output signal simultaneously by this.
In the complex logic computing circuit that is used in the past, as, multiple input multiplexer (muxes), multidigit primitive encoding devices etc. often are accompanied by and are used for keeping the buffer that inputs or outputs from computing circuit (evaluation circuits).In general, these buffers are all relevant with the demand of holding time with setting-up time, and these two kinds of demands all can limit the computing circuit in the prime.In addition, buffer also has the time response of corresponding clock pulse-output (clock-to-output) relation, the computing circuit in the same meeting restriction back level.Therefore, " speed " of buffer is to judge according to the time relationship of its data-output (data-to-output) basically, that is, add that by its setting-up time the temporal summation of clock pulse-output is judged.
If use a traditional buffer circuit in the front and back end of a logical operation circuit, then can in a pipeline system, cause delay, the result of its accumulation will cause operation rate obviously to be slowed down.Wherein, causing a remarkable source in these delays is the demand that comes from setting-up time, and this demand is to satisfy logical operation circuit to guarantee stablizing of temporary output.Therefore, be necessary to reduce these delays so that can increase the extra time in each class, can therefore promote the overall rate of this pipeline system simultaneously.Again, other is necessary to make the characteristic optimization of pipeline system, makes it can provide better usefulness in polynary operating environment widely.
Summary of the invention
According to a kind of dynamic logic buffer of a preferred embodiment provided by the present invention, it comprises: the complementary pair of arithmetic element (complementary pair), and the delayed backward logical circuit, the dynamic calculation device, latch-up logic circuit and is kept circuit.The complementary pair of this arithmetic element is corresponding to a clock pulse signal and provides a precharge node and a compute node.This delayed backward logic receives this clock signal and exports one and finish signal, and this finishes signal is that one of this clock signal postpones and reverse form.This dynamic calculation device is coupled between this precharge node and this compute node, and between the operational stage between next operation edge that an operation edge and this of this clock signal are finished signal, calculates a kind of logical function according at least one input data signal.And corresponding to clock pulse and the latch-up logic circuit of finishing signal and precharge node state, the state that can make an output node is decided by the state of this precharge node between operational stage, in addition, this precharge node of nip (clamp) of still needing is sent to output node with the fluctuation that prevents data-signal.This holding circuit is coupled to output node so that keeping the state of this output node when this output node is in three-state (Tri-State), or makes this output node not be driven to a particular logic state.
In various embodiment, the complementary pair of arithmetic element comprises and draws element (Pull-up Device) and N-passage drop down element (Pull-down Device) on the P-passage.This dynamic calculation device can be very simple circuit or very complicated circuit.This dynamic logic buffer comprises one output buffer/reverser, and this output buffer/reverser has the output that an input and that is coupled to output node is coupled to reverse output node.
Implement in the configuration one, this latched logic comprises a N-passage transmitting element (Pass Device), draws element on the first and second P-passages, and a nip (clamp) element and piles up (stack) by the formed weak point of N-passage drop down element.This N-passage transmitting element comprises: a gate, and it receives the above-mentioned signal of finishing, and a drain and source electrode, and it is coupled on this precharge node and one and draws between the Control Node.Draw element to comprise on the one P-passage: a gate, it receives the above-mentioned signal of finishing, and a drain and source electrode, and it is coupled in source voltage and is somebody's turn to do and draws between the Control Node.Draw element to comprise on the 2nd P-passage: a gate, it is coupled to and draws Control Node on this, and a drain and source electrode, and it is coupled between source voltage and this output node.This nip element is coupled between this precharge node and this compute node and corresponding to this and finishes signal, makes precharge node nip (clamp) to this compute node in order to finish at this when signal is in the accurate state in low (low) position.
Short N-passage drop down element of piling up is coupled between output node and the ground connection and by clock signal and precharge node to be controlled.This nip element can comprise: a reverser, this reverser have an output and and are coupled to the input that this finishes signal; One N-passage nip element, it has a drain and a source electrode that is coupled between this precharge node and this compute node, and a gate, and it is coupled to the output of this reverser.Short N-passage drop down element of piling up comprises the first and second N-passage laminated components.The one N-passage laminated components comprises: one in order to receive the gate of this clock signal, and one is coupled to the drain and the one source pole of this output node.The 2nd N-passage laminated components comprises: one is coupled to the gate of this precharge node, and a drain and that is coupled to the source electrode of a N-passage drop down element is coupled to the source electrode of ground connection (ground).
Dynamic latch circuit according to one embodiment of the invention comprises: a dynamic circuit, and a delayed backward device, a latch circuit and is kept circuit.This dynamic circuit carries out precharge to first node and drag down the position at Section Point place when this clock signal proceeds to high levels accurate when clock signal is low level, carry out the state of the computing of first logical function with the control first node by this.This delayed backward device receives this clock signal and a delayed backward clock signal is provided.The state that this latch circuit impels an output node is controlled by the state of first node between operational stage, be when starting from this clock signal and proceeding to high levels between wherein so-called operational stage and when ending at this delayed backward clock signal and proceeding to low level, in addition, but still this first node of nip to isolate this output node.
In these cases, this latch circuit can comprise the first and second N-pass elements, a reverser, and a P-pass element and piles up element.The one N-pass element makes the 3rd node be coupled to first node when this delayed backward clock signal is high levels.This reverser receives this delayed backward clock signal and provides one to postpone clock signal.The 2nd N-pass element makes first node couple mutually with Section Point when this delay clock signal is high levels.This P-pass element is drawn high the 3rd node when this delayed backward clock signal is low level.This laminated components is drawn high this output node when the 3rd node is low level and between operational stage when if first node is high levels this output node is dragged down.This laminated components comprises the 2nd P-pass element and the three, the four N-pass element.The 2nd P-pass element is drawn high this output node when the 3rd node is low level.The the 3rd and the 4th N-pass element is a coupled in series between this output node and ground connection, in order to when this clock signal and first node all are high levels this output node is dragged down.
Method according to the disclosed a kind of dynamically temporary output signal of one embodiment of the invention comprises: when the clock pulse signal is low level first node is carried out precharge, when the clock pulse signal proceeds to high levels, discharge (Release) first node and drag down Section Point, when being in high levels, the clock pulse signal between first and second nodes, calculates the logic state of a kind of logical function with the control first node, this clock signal of delayed backward is to provide a delayed backward clock signal, at the beginning in clock signal changes high levels and ends at the delayed backward clock signal between the operational stage that changes low level, control the logic state of this output node with first node, and the logic state of keeping output node between operational stage, be included in the delayed backward clock signal when being the low level state nip first node to Section Point.
Said method can comprise buffering and reverse this output node.This method comprises: transmit on the logic state to of this first node and draw Control Node, if should on when drawing Control Node to be low level, this output node is drawn high, if when this first node is high levels, this output node is dragged down.This method can comprise: with this output node with should on draw Control Node to isolate, and with the first node nip to low level, the laminated components that is coupled between this output node and the low level node is closed.This method also can comprise: oppositely this delayed backward clock signal to be providing one to postpone clock signal, and when this delay clock signal is the high levels state, drive a N-pass element with the nip first node to Section Point.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is according to the schematic diagram of the dynamic logic buffer of a preferred embodiment of the previous related invention that discloses.
Fig. 2 is according to the schematic diagram of the dynamic logic buffer of a preferred embodiment of the present invention, and it comprises a kind of nip mechanism that makes output node isolate usefulness.
Fig. 3 is the time sequential routine figure that shows the dynamic logic buffer of the 2nd figure.
Fig. 4 is according to the flow chart of a kind of dynamically temporary output signal method of a preferred embodiment of the present invention.
100 dynamic logic buffers, 101,103 nodes
105 dynamic calculation devices, 107 precharge nodes
109 delayed backward logical circuits, 111 circumscription logic circuit
115 add logical circuit 117 compute node
Draw Control Node 12 initial output nodes on 119
123 reversers/buffer 125 holding circuits
The 125A first reverser 125B second reverser
200 dynamic logic circuits, 201,203 nodes
305 unsettled conditions between 301,302,303 operational stages
Embodiment
The following description is under a specific embodiment and necessary condition thereof and provide, and can make generally to have the knack of this operator and can understand to implement the present invention.Yet the various modifications that this preferred embodiment is done are apparent for those who familiarize themselves with the technology, and, in this General Principle of discussing, also can be applied to other embodiment.Therefore, the present invention is not limited to this place and shows specific embodiment with narration, but has the maximum magnitude that principle that place therewith discloses conforms to novel feature.
The inventor of this case recognizes because the required temporary output of logical circuit, its " speed " is the key factor for this logical circuit, and for making whole optimization of design, can by as mode such as the minimizing of component number so that speed increase and make the chip area decline that is consumed.Based on above demand, this case inventor has developed a kind of dynamic logic buffer, it provides required breech lock input of this logical operation function and temporary output, this logical function can be faster than previous configuration and can minimize N-pass element in piling up, gather way by this and reduce element and configuration area on the chip, wherein, this piles up the sampling state in order to rfpa output signal, please refer to Fig. 1 to Fig. 4 is further described, when need to use a kind ofly when making data be sent to the buffer of another class by a class in a large number in a pipeline architecture, the dynamic logic buffer that is provided in the embodiments of the invention can make the operation rate of whole elements speed a lot and the chip layout area is descended.
Fig. 1 is the schematic diagram according to the dynamic logic buffer 100 of a preferred embodiment of the previous related invention that discloses (U. S. application case number be 10/730703).The input of dynamic logic buffer 100 partly comprises a P-pass element P1 and a N-pass element N2, it forms the complementary pair of an arithmetic element, wherein, the source electrode P1 of P1 is coupled to source voltage VDD and its drain is coupled to a precharge node 107 so that a signal TOP to be provided.One dynamic calculation circuit 105 is coupled between the drain of node 107 and N2, and the source electrode of N2 is coupled to ground connection.This dynamic calculation circuit 105 can be a kind of simply as the design of N-pass element, also maybe can comprise more complex calculations Logical Configuration.Under any circumstance, this dynamic calculation circuit 105 drags down this TOP signal to carry out " computing " when clock signal CLK is high levels.Though and only show among the figure single data-signal (DATA) provide to dynamic calculation circuit 105 to calculate, be familiar with this operator and will know that any amount of data-signal all can be used in this calculating process.Wherein, the logical function that this dynamic calculation circuit 105 carried out or calculated, its scope can be very simple or very complicated.
This input clock signal CLK provides to the gate of P1 and N2 via node 101, is sent to the input of delayed backward logical circuit 109 and the gate of N-pass element N5 more respectively.To illustrate in detail that below one is coupled to restriction (Qualifying) logical circuit 111 of delayed backward logical circuit 109.
The DATA input signal is to provide to the input of this dynamic calculation circuit 105 via node 103.In addition, node 107 is coupled to the gate of N-pass element N6, and the drain of N6 then is coupled to the source electrode of N5, and the source electrode of N6 is coupled to ground connection.The drain of N5 is coupled to the source electrode of N-pass element N4, and the drain of N4 is coupled to initial (preliminary) output node 121.The output of this delayed backward logical circuit 109 is coupled to node 117 and finishes signal EC so that a computing to be provided, and wherein compute node 117 is coupled to P2, the gate of N3 and N4.The source electrode of P2 is coupled to VDD.This node 107 is coupled to the source electrode of N-passage transmitting element N3, and the drain of N3 is coupled to draw Control Node 119 on one and provide and draws control signal PC on one.This node 119 is coupled to the drain of P2 and the gate of P3.Adding logic (AdditionalLogic) 115 is coupled between the source electrode of VDD and P3.The drain of P3 is coupled to the drain of N4 and provides an output signal Q on initial output node 121.One keeps circuit 125 is coupled to node 121, this holding circuit 125 comprises one first reverser 125A, its input is coupled to node 121 to receive the input that Q signal and its output are coupled to the second reverser 125B, and the output of this second reverser 125B is coupled to node 121.In one embodiment, this holding circuit 125 is a kind of more weak holding circuits, its need by on draw piling up of element P3 or drop down element N4-N6 to strengthen (Over-powered).
This output node 121 is coupled to the input of reverser/buffer 123, and the output of this reverser/buffer 123 produces a kind of reverse output signal QB." buffering " is favourable to the input that drives next logic OR latch circuit, especially piling up usually of element P3 and N4-N6 this node 121 shown that a kind of three-state and this reverser 125B belong under a kind of situation of more weak element comparatively speaking.This reverser/buffer 123 can be replaced to prevent logic reversal by a noninverting buffer.Yet a non-return buffer is implemented with the reverser of back-to-back (Back-to-Back) usually, may make the delay of not expecting increase and can increase clock pulse to the time of delay of exporting like this.
Person described in the U. S. application case 10/730703 of previous announcement, interconnected each element P2, N3, P3, N4 and this add logical circuit 115 and form the bolt lock mechanism that a kind of TOP signal is used, and its state is to determine between short operational stage between the drop edge of the rising edge of CLK and EC signal.The delayed backward signal that this EC signal is a CLK is to be referenced into a revertive delay clock signal at this.TOP state between operational stage is sent to the PC signal via transmitting element N3.If this dynamic operation logical signal drags down this TOP, then this TOP closes this N6 and this PC makes the P3 conducting.If this adds logical circuit 115 and VDD is provided source electrode to P3 between operational stage, then a kind of logic " high " state can provide to this output signal Q via P3.If this adds logical circuit 115 and closes during this period, even then P3 conducting, the state of Q still remains on the state of before having been set up by this holding circuit 125.After this timing period, this EC proceeds to low level, and N3 and N4 are closed, and P2 connects, and it draws high this PC, therefore P3 is closed and makes this output Q become three-state.This more weak holding circuit 125 makes Q remain on the position standard that it has been calculated after EC proceeds to low level in all the other periods in this clock pulse cycle.
When the EC signal proceeded to low level via the bolt lock mechanism of a binding member N5, representative should be finished in temporary effect.When CLK proceeded to low level (and therefore when EC proceed to high levels and make the N4 conducting), then N5 closed, so can keep the state of reverse output signal QB at the clock pulse of second half cycle in the cycle.During this half cycle, when this EC still kept low level, P3 also can remain closed condition, and output Q then can keep tri-state state.Simultaneously, under the situation that element P1 conducting and N2 close, can make TOP be precharged to a kind of high logic (logic high) state.After this postponed, when EC proceeded to high levels, element N3 conducting allowed this TOP (it is drawn high via P1) keeping a kind of high levels on PC, therefore made P3 keep closing.
This delayed backward logical circuit 109 can be realized with different modes, for example, couples one or more reverser with series system.This circumscription logic circuit 111 combines utilization with delayed backward logical circuit 109, can forbid effectively that the EC signal becomes the accurate state in " height " position when CLK proceeds to high levels, can prevent that like this logical function TOP that has obtained is sent to this output QB via N3.On function, can make the designer maintain the original state of QB in the cycle like this at follow-up clock pulse.
Under polynary operating environment widely, as, by low temperature, low pressure and one can produce in the environment that the process of quick P-pass element and low speed N-pass element represents a kind of, is necessary that characteristic optimization with the dynamic logic buffer is to provide superior performance.And know that in various simulations in being piled up by the storage node isolation that comprises 3 N-pass element N4-N6, it presents a kind of speed of this dynamic logic buffer 100 and chance of performance of improveing.Be familiar with this operator will understand a N-or P-pile up in the reduction of component number can make speed obtain improvement and further cause the saving of material.For example, what notice was known is: when being piled up by 2 component types when proceeding to 3 component types and piling up, if desire in 3 component types pile up, keeping one with identical pull-down strength during 2 component types pile up, then not only need another transistor, and the width of in 3 transistors each element in must piling up than 2 component types is big 1.5 times.Therefore, need more area so that identical pull-down strength to be provided on the chip circuit layout.
Fig. 2 is dynamic logic buffer 200 schematic diagrames of being realized according to a preferred embodiment of the present invention, and it is to represent with identical reference symbol with these dynamic logic buffer 100 components identical and assembly.Reduced by piling up that 2 N-pass elements N5 and N6 are constituted by piling up of being constituted of 3 N-pass element N4-N6, wherein N4 deletes, and directly is coupled to this initial output node 121 by the drain of N5.The node 117 that is loaded with the EC signal provides to the input of reverser U1, and this reverser U1 provides the reverse signal (being called the ECB signal) of a kind of EC on it is positioned at output on the node 201.Because the delayed backward signal that signal EC is CLK is finished in this computing, then this ECB signal is an effective CLK inhibit signal, is referred to as to postpone clock signal.Node 201 is coupled to the gate of a new N-pass element N7, and the drain of this N7 is coupled to the drain that node 107 (this TOP signal) and its source electrode are coupled to N2.The drain of N2 forms a kind of node 203 that sends a computing signal EV.In the means that are similar to dynamic logic buffer 100, the drain of this N2, or EV signal can pull into low level under the quilt, so that carry out computing by dynamic calculation circuit 105 when CLK determines the high levels state.
When this EC signal becomes low level, be necessary to isolate output node 121 Q signal is provided, and being element P3 and N4 by previous dynamic logic buffer 100, reaches this kind isolation features.Rfpa output signal Q be consider in circuit, do not have under the improper operating result by the DATA input signal the interference that may cause.The time that need keep input signal stable usually is referred to as " keeping (the hold) " time.After this retention time expired, the DATA input need not keep stable.In dynamic logic circuit 200, can make piling up of N-pass element drop to 2 elements the N4 deletion by 3 elements, but the mechanism that can't provide a kind of path that N-pass element N5 and N6 are provided to isolate causes output node 121 to isolate with earth terminal.Therefore, if estimation TOP signal is to be in low level, then DATA signal formed any fluctuation after EC becomes low level (and N5 is by the conducting of CLK signal institute) may cause TOP to become to be the high levels state, and the conducting of N6 drags down Q signal output state is worsened.
Yet, a kind of breech lock or strangulation mechanism that reverser U1 and N-pass element N7 set form, can be when the EC signal be in low level with node 107 nips (clamp) to node 203 coordination standards, and make the TOP signal can not become high levels (though DATA has fluctuation to cause), proceed to low level subsequently so that till when next execution cycle carries out precharge to this TOP signal up to CLK.The dynamic logic buffer 200 of this kind Improvement type can guarantee still keeping when the TOP signal drops to low level by EC low level till CLK becomes low level again next time.Therefore, when EC transferred low level to, ECB can become high levels and make the N7 conducting and with the logic state of TOP signal nip to EV.Can during relevant, force the TOP signal to become low level like this, any fluctuation (it may make the TOP signal become high levels in addition) of DATA signal can be absorbed via N-pass element N7 now.Can TOP when becoming low level, EC be discharged in this way, so this output signal Q is isolated in the residue of CLK signal.
Fig. 3 is the time sequential routine figure that shows dynamic logic buffer 200, CLK wherein, and EC, ECB, DATA, TOP, EV, PC, Q and QB signal plot time shaft.When T0, the CLK signal is a low level, makes the precharge of TOP signal become " height " logic level.This EC signal is to be in high levels P2 is closed and to make the N3 conducting at first, so this PC signal is pulled to high levels by this TOP signal at first via N3.Therefore this ECB signal is the reverse state of EC signal, is at first to be in low level and N7 is closed.P3 and N5 close to provide a kind of ternary situation to this Q signal, promptly keep Q signal state formerly by holding circuit 125.In described situation, Q signal is to be in logic when T0 at first " height " state, and the QB signal is to be in the low level state, the DATA signal is to be in the high levels state at first.Shown in special configuration in, this dynamic calculation circuit 105 can effectively couple node 107 and 203 when the DATA signal is in high levels.Therefore, even N2 closes when CLK is in low level, the TOP signal also can be drawn high the EV signal via this dynamic calculation circuit 105 at first.
Be to start from each rising edge of CLK signal and the drop edge of ending at delayed backward clock signal EC between operational stage.Period between this operational stage is by delayed backward logical circuit 109 " retardation " define.This CLK signal rises at next time point T1, P1 is closed and make N2 and the N5 conducting with initialization just like between first operational stage shown in the label 301.And this EV signal is dragged down when the N2 conducting.The state of TOP signal between operational stage depends on the computing that 105 pairs of these DATA signals of this dynamic calculation circuit are carried out.Shown in the embodiment of dynamic calculation circuit 105 in, this DATA signal is in high levels when time T 1 makes dynamic calculation circuit 105 carry out computing so that 301 the TOP signal dragged down between operational stage, so N6 is closed.Because the EC signal 301 is still keeping high levels between operational stage, so the state of TOP is sent to the PC signal via N3, equally also makes the PC signal become low level and make the P3 conducting.Suppose that this adds logical circuit 115 and VDD is provided source electrode to P3 between operational stage, then Q signal can be drawn high (or still keeping high levels) and the QB signal can be dragged down (or still keeping low level).
When T2 because the timing period of this delayed backward logical circuit 109 expires, then the EC signal become low level and make that N3 closes, P2 conducting and make between this operational stage 301 to finish.The ECB signal become that high levels makes the N7 conducting and with node 107 nips to node 203, EV drags down the TOP signal when making the N2 conducting.The PC signal is drawn high by VDD via P2 again, and P3 is closed.Because CLK is in high levels, then N5 is keeping conducting.When DATA kept high levels, the TOP signal was in low level and keeps N6 and close, so this Q signal is isolated.Be at CLK during the T3 half period of high levels, the DATA signal becomes low level.Though N2 is conducting still, depend on the special composition of dynamic calculation circuit 105, cause the state of TOP signal not determine, cause the fluctuation of DATA signal may unexpectedly impel the TOP signal to become high levels.Though reverser U1 draws high ECB and make the N7 conducting in rest period, yet maintenance low level and the N6 of TOP close, and make Q still keep isolation.In this mode, the fluctuation of DATA signal will can not threaten and Q signal is dragged down.This holding circuit 125 can make Q signal keep high levels in CLK is the rest period of high levels, and that reverser 123 can make the QB signal remain on logic " low " position is accurate.
In later time T4, a drop edge of CLK signal takes place, cause N2 to close and P1 replys the state of conducting, precharge becomes high levels so the TOP signal is once more via the VDD of P1.When T4 became low level, N5 closed at the CLK signal, even make that this TOP draws high and conducting N6, this output node 121 is still keeping isolation.Because CLK N2 when time T 4 becomes low level closes, and makes the N7 conducting owing to ECB is still high levels, TOP is no longer dragged down by EV, and relatively, EV is but drawn high by TOP.When time T 5 became high levels, the N3 conducting made the high levels of TOP be sent to the PC signal via this transmitting element N3 again at the EC signal, and this moment, this PC signal kept high levels and P3 to close.Close because DATA is low level and N2 and N7, therefore after time T 5, CLK is the rest period period of low level, and as label 305 those shown, the state of EV is uncertain.Though EV was still keeping the high levels state owing to before be driven into high levels, and also may be because of being disturbed by the height of DATA and being driven into high levels, the state of this EV is still illogical in during this period of time.
When the rising edge of CLK signal during in time T 6 begins, be identical basically in the operation.Yet in such cases, this DATA signal (it is a high levels when the last rising edge of CLK signal) is a low level and greatly about determine to become high levels during in time T 6 during identical time with this CLK signal.When the EC signal becomes low level, by time T 6 between second operational stage of next time T 7, because the DATA signal is a high levels, therefore the DATA signal can be operated correctly with the time of filling part by this dynamic calculation circuit 105 and calculate, and makes Q and QB signal can be specified to correct state.In this mode, can know this setting-up time under the initial operation time of transfer time of DATA signal and CLK situation much at one even be familiar with this operator, still can successfully calculate its value because of logical function is an effective value zero.To between the 3rd operational stage between the next drop edge time T 9 of EC signal, shown in label 303, operational circumstances is similar in the next rising edge of CLK signal time T 8.Yet in such cases, the DATA signal is to set low logic level for, impels this dynamic calculation circuit 105 can't carry out computing, and makes the TOP signal keep high levels, and N6 keeps conducting state.Because the EC signal is still keeping high levels, then the high levels state of N3 conducting and this TOP can be sent to the PC signal and P3 is closed.This CLK signal makes the N5 conducting, and because TOP is still keeping high levels, then Q signal piles up via drop down element N5 and the formed weak point of N6 when time T 8 greatly and is discharged to low logic level, and this QB signal is also set high levels for by reverser 123 greatly when time T 8.When the EC signal becomes low level and when making between this operational stage 303 to finish, this PC signal is drawn high (or keeping high levels) by VDD via P2, P3 is closed in time T 9.Though DATA is keeping when time T 9 that this TOP signal still can keep high levels under the situation of low level, this TOP signal still via N7 by the EV nip to low level, this is to cause because of the ECB signal becomes high levels.Therefore, 303 at the expiration the time between this operational stage, and P3 and N6 element provide a kind of ternary situation to Q signal again.Be similar to previous described mode, keeping the state of Q signal in the period in the residue in this cycle by this holding circuit 125.In this kind mode, this Q and QB signal between operational stage, can switch and the clk cycle after this computing period expiration during in still can keep stable state.
When the EC signal via element P2, P3, N3, N5, N6, formed breech lock of N7 and U1 and nip logical circuit and when becoming low level, when each computing period expiration, should temporary function finish.This EC signal becomes low level can be made N3 close and make the P2 conducting, and P2 can draw high the PC signal P3 is closed, and the TOP signal is dragged down by N7 via ECB.Therefore, in the first preceding half arteries and veins cycle when the CLK signal is high levels, Q signal can be by drawing element P3 on this and piling up isolation by drop down element N5 and the formed weak point of N6.Become low level when beginning second half cycle in this clock pulse cycle at the CLK signal, N5 can close and when the EC signal is still keeping low level and P3 also to keep closing, then can keep Q signal (its still by on draw with drop down element keeping isolation) state.Simultaneously, the conducting of P1 and N2 close, and can cause this TOP signal to be precharged to high levels.When the EC signal became high levels, the N3 conducting allowed the high levels state of TOP signal to be sent to the PC signal, so make P3 keep closing.When being begun between next operational stage by each computing period expiration, the state of this Q and QB signal is being kept by this holding circuit 125 and irrelevant with the variation of input data signal.
This function that adds logical one 15 circuit is to ignore or prevent to have on the Q signal logic output of high levels.This circumscription logic circuit 111 couples or combines with delayed backward logical circuit 109, so that forbid effectively that when the CLK signal becomes high levels the EC signal becomes high levels, can prevent that like this TOP signal of representing the arithmetic logic function can not be sent to output QB via N3.Such function can make a designer can keep the original state of Q and QB signal where necessary at follow-up clock pulse in the cycle.
Fig. 4 is the method flow diagram according to a kind of dynamically temporary output signal of a preferred embodiment of the present invention.Operation starts from the step 401, and when clock signal was low level, first node can be by pre-charge.In step 403, when the clock pulse signal is transferred to high levels when opening the computing of a logical function, as, when dynamic calculation circuit 105 is determined to be high levels at this clock signal, in the time of can carrying out a kind of computing of logical function according to one or more input data signal, first node can be released (released) and Section Point is dragged down to control the logic state of first node.In step 405, this clock signal is delayed and is reversed to provide a kind of delayed backward clock signal.For example, this delayed backward logical circuit 109 with this CLK signal delay so that EC to be provided signal.This clock pulse postpone during can be set so that a kind of minimum delay required when guaranteeing that this logical function is finished by calculating to be provided.In the lock-in tube line structure, as, in a kind of pipeline type microprocessor or similar articles, the delay of class can change according to the pairing logical function of each grade.Another way be can according to the time demand decision of minimum general time of delay with during calculating the longest required in each class logical operation.Between a kind of operational stage of being set up during this delay, originate in the operational branchpoint (for example, the rising edge of CLK) of this clock signal, and with respect to next branchpoint (for example, EC drop edge next time) of this delayed backward clock signal.
In step 407, the logic state of this output node is to control according to the logic state of the first node that is determined between operational stage.Please refer to this dynamic logic buffer 100, if TOP is keeping the high levels state between operational stage, then Q signal can be become low level by breech lock, but if TOP moves the low level state between operational stage, then Q signal can be become the high levels state by breech lock.In step 409, the logic state of this output node (for example, Q signal) can kept between the beginning between computing period expiration and next operational stage.This is included between operational stage or at least between CLK signal next time step-down, the strangulation first node to Section Point to isolate this output node from first node.In an illustrated embodiment, can provide one to postpone clock signal ECB by the EC signal that U1 oppositely formed, it can make the N7 conducting after finishing between this operational stage.Till TOP can being dragged down like this when CLK becomes low level again next time, so this laminated components N6 is closed and isolate this output node.In this mode, in case after logic state determined when each computing period expiration, output state promptly can be maintained up between next operational stage, to guarantee the integrality of output signal, no matter whether input data signal changes.In step 411, buffering and reverse this output node are to drive input subsequently.
Dynamic logic buffer according to a preferred embodiment of the present invention, it provides the capable of being combined property of a kind of dynamic circuit in speed and computing, it not only effectively reduces holding time of input data, simultaneously also make buffer have the dateout retention characteristic, more show a kind of zero setting-up time in addition, one very short extremely short clock pulse-output time of retention time and one, another kind is a lot of soon in the configuration that logical calculated device front and back all are provided with latch unit therefore to make this design.The delayed backward signal of one CLK (for example, the EC signal) and can provide between a kind of short operational stage during the combination of breech lock and nip mechanism, can allow the output (for example, TOP signal) of this dynamic calculation device to be sent to initial output node (for example, Q signal) between this operational stage.After between this operational stage, each exports laminated components (for example, P3, N5, N6) operation together in the half period of the residue when this CLK signal is high levels, and in the half period when the CLK signal is low level and high levels subsequently, ternary situation is provided to this initial output node.U1 and N7 form a kind of nip circuit so that TOP keeps low level, helps the isolation of this output node like this, and can delete the N-pass element in piling up configuration, shows optimized usefulness so that make in polynary operating environment widely.Particularly, the N-pass element of less (for example, narrower) can be used to make short pull-down strength identical when piling up (two elements) and keeping with three elements.Simultaneously, also can gather way and reduce area on the chip configuration.
According to the dynamic logic temporary storage mechanism that a preferred embodiment of the present invention is provided, also can provide a kind of breech lock and temporary function of output imported to the logical calculated function of complexity.In addition, because the present invention can eliminate and be common in setting-up time required in the LATCH-LOGIC-LATCH configuration, therefore the time response of data-output is obviously reduced.So that the complicated logical operation function provides breech lock input and temporary output, configuration that can be more present is a lot of soon to simple for the dynamic logic temporary storage mechanism.When being used in when need relying on a large amount of buffers the data one-level being passed the pipeline architecture of one-level, the present invention can make the operation rate of integral member increase widely.
Though the present invention does detailed description with preferred embodiment, other preferred embodiment and variation also are possible and to be expected.For example, the dynamic calculation circuit can be designed to simply on demand or be very complicated.In addition, the circumscription logic circuit with add that logical circuit also can omit or realized to be familiar with any suitable mode that present technique field person can recognize.In addition, though the disclosed execution mode of the present invention is the element that utilizes metal-oxide semiconductor (MOS) kenel, it has comprised the complementary metal oxide semiconductor element, as NMOS and PMOS transistor etc., precisely because still can utilize the technology kenel and the framework of similar aspect or analogy to implement, for example dual-polarity elements or similar elements or the like.
Claims (18)
1, a kind of dynamic logic buffer is characterized in that it comprises:
One arithmetic element complementary pair is corresponding to a clock pulse signal and provide a precharge node and a compute node;
One delayed backward logical circuit is in order to receive this clock signal and to export one by this clock signal delay and the signal of finishing that oppositely forms;
One dynamic calculation device, it is coupled between precharge node and this compute node, between the operational stage between next edge that running edge and this of this clock signal are finished signal in, come computing one logical function according at least one input data signal;
One latch-up logic circuit, corresponding to this clock signal, this finishes the state of signal and this precharge node, be the state of an output node to be decided between this operational stage by the state of this precharge node, this precharge node of nip is sent to this output node with the fluctuation that prevents at least one data-signal; And
One keeps circuit, and it is coupled to this output node.
2, dynamic logic buffer according to claim 1 is characterized in that wherein said arithmetic element complementary pair comprises:
One P-pass element has a gate that is used for receiving this clock signal, and one is coupled in drain and the source electrode between one source pole voltage and this precharge node; And
One N-pass element has a gate that is used for receiving this clock signal, and one is coupled in drain and the source electrode between this compute node and the earth terminal.
3, dynamic logic buffer according to claim 1 is characterized in that wherein said latched logic comprises:
One N-passage transmitting element has one and is used for receiving the gate that this finishes signal, and one is coupled in drain and the source electrode that draws on this precharge node and between the Control Node;
Draw element on one the one P-passage, have one and be used for receiving the gate that this finishes signal, one is coupled in one source pole voltage and is somebody's turn to do drain and the source electrode that draws between the Control Node;
Draw element on one the 2nd P-passage, have one and be coupled to the gate that draws Control Node on this, one is coupled in drain and the source electrode between one source pole voltage and this output node;
One nip element is coupled between this precharge node and this compute node and corresponding to this and finishes signal, in order to finish at this signal when the low level this precharge node of nip to this compute node; And
One short stack N-passage drop down element is coupled between this output node and the earth terminal, and is controlled by this clock signal and this precharge node.
4, dynamic logic buffer according to claim 3 is characterized in that wherein said nip element comprises:
One reverser has an input and an output, and this input is coupled to this and finishes signal; And
One N-passage nip element comprises that one is coupled in drain and the source electrode between this precharge node and this compute node, and one is coupled to the gate of the output of this reverser.
5, dynamic logic buffer according to claim 3 is characterized in that wherein said short stack N-passage drop down element comprises:
One the one N-passage laminated components comprises that one is used for receiving the gate of this clock signal, and one is coupled to the drain and the one source pole of this output node; And
One the 2nd N-passage laminated components comprises that one is coupled to the gate of this precharge node, and a drain and that is coupled to the source electrode of a N-passage drop down element is coupled to the source electrode of earth terminal.
6, dynamic logic buffer according to claim 3 is characterized in that comprising more that wherein one adds logical circuit, is coupled on source voltage and the 2nd P-passage and draws between the element, in order to prevent the selected state of this output node.
7, dynamic logic buffer according to claim 1 is characterized in that wherein more comprising one output buffer/reverser, has an output that is coupled to the input of this output node and is coupled to a reverse output node.
8, a kind of dynamic latch circuit is characterized in that it comprises:
One dynamic circuit carries out precharge to first node when clock signal is low level, and when clock signal transfers high levels to Section Point is drawn high, so that calculate the state that a logical function is controlled first node;
One delayed backward device is in order to receive this clock signal and a delayed backward clock signal is provided;
One latch circuit, be coupled to this dynamic circuit and this delayed backward device, in order at the beginning in this clock signal transfers the high levels state to and ends between operational stage that next revertive delay clock signal transfers the low level state to, the state of one output node is controlled by the state of first node, and this first node of nip is to isolate this output node; And
One keeps circuit, is coupled to this output node.
9, dynamic latch circuit according to claim 8 is characterized in that wherein said dynamic circuit comprises:
One P-pass element is in order to carry out precharge to first node when this clock signal is low level;
One logical circuit is coupled between first and second nodes, in order to calculate this logical function;
One N-pass element is coupled to this Section Point, calculates this logical function in order to make this logical circuit when this clock signal becomes high levels.
10, dynamic latch circuit according to claim 8 is characterized in that wherein said latch circuit comprises:
One the one N-pass element is in order to couple one the 3rd node to this first node when this delayed backward clock signal is high levels;
One reverser is in order to receive this delayed backward clock signal and to provide one to postpone clock signal;
One the 2nd N-pass element is in order to be coupled in together this first node and Section Point when this delay clock signal is high levels;
One the one P-pass element is in order to draw high the 3rd node when this delayed backward clock signal is low level; And
One piles up element, is coupled to this output node, when the 3rd node is low level this output node is drawn high and when this computing is high levels as if first node therebetween this output node is dragged down.
11, dynamic latch circuit according to claim 10 is characterized in that wherein said laminated components comprises:
One the 2nd P-pass element, it is drawn high this output node when the 3rd node is low level; And
One the 3rd and one the 4th N-pass element is to be coupled between this output node and the earth terminal with series system, in order to when this clock signal and first node all are high levels this output node is dragged down.
12, dynamic latch circuit according to claim 8 is characterized in that it comprises that more one adds logical circuit, is coupled to this latch circuit, to prevent a logic state of being scheduled to of this output node.
13, a kind of method of dynamically temporary output signal is characterized in that it comprises:
When a clock pulse signal is low level, the precharge first node;
When this clock signal becomes high levels, discharge (Release) first node and drag down Section Point;
One logical function that is coupled between first and second nodes is carried out computing, and this logical function is controlled the logic state of first node when clock signal is high levels;
Postpone to reach reverse this clock signal so that a delayed backward clock signal to be provided;
At the beginning when this clock signal changes into high levels and in ending between operational stage that next this delayed backward clock signal changes into low level, control the logic state of an output node with first node; And
Keep the logic state of this output node between between each operational stage, comprise that when this delayed backward clock signal was low level, this first node of nip was to Section Point.
14, the method for dynamically temporary output signal according to claim 13 is characterized in that wherein more comprising buffering and reverse this output node.
15, the dynamically method of temporary output signal according to claim 13 is characterized in that wherein keeping the logic state of this output node comprising that coupling one keeps circuit to this output node.
16, the dynamically method of temporary output signal according to claim 13 is characterized in that wherein the logic state of controlling this output node with first node comprises:
Transmit on the logic state to of this first node and draw Control Node;
If when drawing Control Node to be low level on being somebody's turn to do, the position of drawing high this output node is accurate; And
When if first node is high levels, the position that drags down this output node is accurate.
17, the method for dynamically temporary output signal according to claim 16 is characterized in that the logic state of wherein keeping this output node comprises:
Draw Control Node on isolating this output node and being somebody's turn to do; And
This first node to one low level state of nip is to close the laminated components that is coupled between this output node and the low level node.
18, the method for dynamically temporary output signal according to claim 17 is characterized in that wherein this first node of nip to low level comprises:
Oppositely this delayed backward clock signal is to provide one to postpone clock signal; And
When this delay clock signal is high levels, drive a N-pass element with this first node of nip to Section Point.
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| Application Number | Priority Date | Filing Date | Title |
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| US10/925,307 | 2004-08-24 | ||
| US10/925,307 US7212039B2 (en) | 2003-08-27 | 2004-08-24 | Dynamic logic register |
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| CN100373775C CN100373775C (en) | 2008-03-05 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101894011A (en) * | 2009-08-13 | 2010-11-24 | 威盛电子股份有限公司 | The method of the state of working storage, integrated circuit and a temporary input end |
| CN101924546A (en) * | 2009-09-09 | 2010-12-22 | 威盛电子股份有限公司 | Rapid dynamic register and related integrated circuit and data temporary storage method |
| CN103714860A (en) * | 2013-04-24 | 2014-04-09 | 威盛电子股份有限公司 | Fast dynamic register, registering method, and integration circuit |
| CN106953617A (en) * | 2016-01-06 | 2017-07-14 | 创意电子股份有限公司 | Current-mode logic latch circuit |
| CN107093446A (en) * | 2013-05-28 | 2017-08-25 | 南亚科技股份有限公司 | The clock control method of dynamic random access memory means |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8013649B2 (en) * | 2009-09-01 | 2011-09-06 | Via Technologies, Inc. | Dynamic clock feedback latch |
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| US5075386A (en) * | 1990-04-12 | 1991-12-24 | Eastman Kodak Company | Cross-linkable hot-melt adhesive and method of producing same |
| US6549038B1 (en) * | 2000-09-14 | 2003-04-15 | University Of Washington | Method of high-performance CMOS design |
| US6498514B2 (en) * | 2001-04-30 | 2002-12-24 | Intel Corporation | Domino circuit |
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- 2005-08-08 TW TW94126668A patent/TWI300652B/en active
- 2005-08-18 CN CNB2005100906996A patent/CN100373775C/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101894011A (en) * | 2009-08-13 | 2010-11-24 | 威盛电子股份有限公司 | The method of the state of working storage, integrated circuit and a temporary input end |
| CN101894011B (en) * | 2009-08-13 | 2013-07-24 | 威盛电子股份有限公司 | Temporary memory, integrated circuit and method for temporarily storing the state of an input end |
| CN101924546A (en) * | 2009-09-09 | 2010-12-22 | 威盛电子股份有限公司 | Rapid dynamic register and related integrated circuit and data temporary storage method |
| CN101924546B (en) * | 2009-09-09 | 2012-08-22 | 威盛电子股份有限公司 | Rapid dynamic register and related integrated circuit and data temporary storage method |
| CN103714860A (en) * | 2013-04-24 | 2014-04-09 | 威盛电子股份有限公司 | Fast dynamic register, registering method, and integration circuit |
| CN103714860B (en) * | 2013-04-24 | 2016-05-11 | 威盛电子股份有限公司 | Dynamic register, register method, integrated circuit fast |
| CN107093446A (en) * | 2013-05-28 | 2017-08-25 | 南亚科技股份有限公司 | The clock control method of dynamic random access memory means |
| CN106953617A (en) * | 2016-01-06 | 2017-07-14 | 创意电子股份有限公司 | Current-mode logic latch circuit |
| CN106953617B (en) * | 2016-01-06 | 2020-07-14 | 创意电子股份有限公司 | Current-mode logic latch circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200608704A (en) | 2006-03-01 |
| TWI300652B (en) | 2008-09-01 |
| CN100373775C (en) | 2008-03-05 |
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