CN100409174C - Dynamic logic register - Google Patents

Abstract

A dynamic logic register including a dynamic circuit, a delayed inverter, a latching circuit, and a keeper circuit. The dynamic circuit pre-charges a pre-charged node while a clock signal is low and evaluates a logic function to control the state of the pre-charged node when the clock goes high. The delayed inverter provides an inverted and delayed clock. The latching circuit controls the state of an output node based on the pre-charged node during an evaluation period beginning when the clock goes high and ending when the inverted delayed clock next goes low. The latching circuit presents a tri-state condition to the output node and the keeper circuit maintains the state of the output node between evaluation periods. The register is very fast with zero setup and short data-to output-time, and may be used between stages in a pipeline system.

Description

Dynamic logic register

The mutual reference of related application

The application of the application's case right of priority is according to U.S. patent application case, case number: 60/432696, and the applying date is on Dec 10th, 2002.

The present invention is relevant with the U.S. patent application case in the following common trial of applying for simultaneously, its applying date with the application's case is identical, and the present invention has the common assignee of list of references and at least one common inventor in position therewith, and comes as list of references in conjunction with its whole content and purpose.

U. S. application case number	The U. S. application date	Exercise question
			10/730703	2003/12/5	The locking mechanism of dynamic logic return-to-zero (DYNAMIC LOGIC RETURN-TO-ZERO LATCHING MECHANISM)

Technical field

The present invention particularly exports the dynamic logic register that the logical operation function is provided relevant for a kind of at depositing relevant for the function of a kind of dynamic logic and register.

Background technology

Integrated circuit has used a large amount of registers, and particularly those have the register of a synchronous line construction.Deposit logic and be used for making the output of element and circuit to keep a period of time, so that these outputs can be received by other element and circuit.In a clock system, a pipeline microprocessor (Pipeline Microprocessor) for example, its register is used for locking (latch) given pipeline and output signal, and keep one section clock cycle period of this output (Clock Cycle) simultaneously, so that the input circuit in the back level can receive last output signal when this given pipeline stages just side by side produces a new output.

In the past, in the complicated logical operation circuit, after before for example multiple input multiplexer (muxes), the multidigit scrambler etc., often utilize register to keep and desire to enter the input signal of computing circuit (evaluation circuits) and the signal of exporting from computing circuit.In general, the requirement that these registers all have related setting-up time and hold time, and these two kinds of requirements all can limit the computing circuit in the prime.In addition, register also has the time response of data-output (data-to-output), and it can limit the computing circuit in the level of back.The speed of exemplary register is judged the time according to its data-output, that is its setting-up time adds the time of clock-output.

Use the legacy register circuit to produce delay in a pipeline system in back before the logical operation circuit, the result of its accumulation will cause operating speed obviously to be slowed down.More particularly, in these postponed, a significant source was the demand of setting-up time, and it must satisfy logical operation circuit to guarantee the stable output of depositing.Therefore, be necessary to reduce these and postpone, so that increase the extra time in each grade, and then promote the speed of whole pipeline system.

Summary of the invention

One embodiment of the invention provide a dynamic logic register, and it comprises the complementary elements, a dynamic evaluator, a delayed backward logic, the locking logic and that correspond to a clock signal and keeps circuit.This dynamic evaluator is coupled on the precharged node between the complementary elements, and comes computing one function according at least one input data signal.This delayed backward logic can be accepted clock signal and export a computing complete signal, and this signal is that one of this clock signal postpones and reverse form.This locking logic corresponds to the state of this clock signal, this computing complete signal and this precharged node, and should locking logic can be during an execution cycle in, control the state of an output node according to this precharged node state, wherein this execution cycle is between next edge of this clock signal one running edge and this computing complete signal.In addition, between each execution cycle, this locking logic shows that a three-state (Tri-State) state is to this output node.And this holding circuit is coupled to this output node to keep the state of this output node between each execution cycle.

Can use P passage and N pass element to implement the some of dynamic logic register, for example, a complementary pair of operand spare can comprise a P passage and a N pass element.This locking logic can comprise draws element and N passage drop down element on the P passage.This dynamic evaluator can comprise a logical circuit in order to the selected function of computing one, and this selected function can very simply also can be very complicated.This delayed backward logic can be the link (Chain) of one or more reverser, and its processing procedure according to special time parameter and use decides.Circumscription logic and/or add logic and can be used to supspend the running of this register or keep an output or prevent the selected state exported.One output buffer/reverser can provide output terminal in order to cushion this output signal.

In a specific embodiment, the locking logic comprises a plurality of P passages and N pass element to carry out needed lock function.For instance, in one embodiment, this locking logic comprises and draws (P-channel Pull-up Devices) element, and a plurality of N passage drop down element (N-channelPull-down Devices) on a N passage transmitting element (N-channel Pass Device), first and second P passage.N passage transmitting element has a grid and is coupled to this precharged node and one source pole and is coupled to and draws Control Node on one in order to receive computing complete signal, a drain electrode.Drawing element to have a grid on the one P passage is coupled to a voltage source and one source pole and is coupled to and draws Control Node on this in order to receive computing complete signal, a drain electrode.Draw element to have a grid on the 2nd P passage, it is coupled to and draws Control Node on this, a drain electrode is coupled to this voltage source and one source pole is coupled to this output node.These a plurality of N passage drop down element are coupled between this output node and the earth terminal, and are controlled by this computing complete signal, this clock signal and this precharged node.

Another embodiment of the present invention discloses a kind of dynamic lock-in circuit, and it comprises a dynamic circuit, a delayed backward device, a lock-in circuit and and keeps circuit.When a clock signal is low level, this dynamic circuit meeting preliminary filling one first node, and when this clock signal transferred high levle to, this dynamic circuit meeting computing one function was to control the state of this first node.This delayed backward device is in order to receive this clock signal and a reverse clock signal that postpones is provided.This lock-in circuit is controlled the state of an output node according to the state of this first node during an execution cycle, wherein this execution cycle and finishes when this delayed backward clock signal transfers low level to next time when this clock signal transfers high levle to.In addition, this lock-in circuit shows that a tri-state state is to output node.This holding circuit is coupled to this output node to keep the state of this output node in during this tri-state state.

Further embodiment of this invention discloses a kind of method of dynamically depositing an output signal, and it comprises a default first node when a clock signal is one first logic state; When this clock signal changed one second logic state into, dynamically computing one function was to control the logic state of this first node; Postpone also reverse this clock signal and a delayed backward clock signal is provided; During an execution cycle, the logic state that is determined during this period according to this first node locks the logic state of output node, wherein this execution cycle is when this clock signal transfers this second logic state to, and finishes when next corresponding conversion of this delayed backward clock signal; And the logic state of between each execution cycle, keeping this output node.

Description of drawings

Figure 1A is the synoptic diagram of an example dynamic circuit of explanation one dynamic circuit feature;

Figure 1B is the clock figure of the dynamic circuit running of explanation Figure 1A;

Fig. 2 A is the synoptic diagram according to the dynamic logic register in one embodiment of the invention;

Fig. 2 B is the clock figure of the dynamic logic register running of key diagram 2A;

Fig. 3 is the synoptic diagram of a simple and easy Fast Dynamic register, the running and the similar of the dynamic logic register of itself and Fig. 2 A; And

Fig. 4 is according to the method flow diagram of dynamically depositing an output signal in one embodiment of the invention.

Symbol description among the figure:

100 dynamic circuits

101 provide the node of a clock signal

103 provide the node of a data-signal

105 provide the precharged node of signal signal HI

107 reversers/impact damper

109 provide the node of an output signal

111 holding circuits

111A first reverser

111B second reverser

200 dynamic logic registers

201 provide the node of a clock signal

203 provide the node of data-signal

205 dynamic evaluators

207 provide the precharged node of top signal

209 delayed backward logics

211 circumscription logics

213 locking logics

215 add logic

217 provide the node of a computing complete signal

219 provide the Control Node of drawing control signal on

221 provide the output node of an output signal

223 reversers/impact damper

225 holding circuits

225A first reverser

225B second reverser

231 first execution cycles

233 shadow regions

235 second execution cycles

237 the 3rd execution cycles

300 simple and easy Fast Dynamic registers

Five reversers of 301 1 groups of series connection

401,403,405,407,409,411 steps

Embodiment

The following description, under the train of thought of specific embodiment and necessary condition thereof and provide, can make general those who familiarize themselves with the technology can utilize the present invention.Yet the various modifications that this preferred embodiment is done are apparent for those who familiarize themselves with the technology, and, in this General Principle of discussing, also can be applied to other embodiment.Therefore, the present invention is not limited to this place and shows specific embodiment with narration, but has the maximum magnitude that principle that place therewith discloses conforms to novel feature.

The inventor of this case realizes and is used for the demand of depositing output (Registered Output) that apparent velocity is the logical circuit of key factor, therefore it proposes a dynamic logic register then, it is for simply locking input (Latched Input) being provided and depositing output to the complicated logical operation function, and also quicker than existing register framework significantly, will further in Fig. 1 to Fig. 4, describe in detail.Highly rely on register and data are sent in the pipeline structure between circuit at different levels when the disclosed a kind of dynamic register of the present invention is used in one, it can make the running speed of single unit system significantly promote.

Figure 1A is the synoptic diagram of an example dynamic circuit 100 of explanation one dynamic circuit feature.This dynamic circuit comprises an input end part of being made up of the P passage P1 of storehouse and N pass element N1, N2.P pass element P1 and N pass element N2 are a complementary pair of operand spare, and N pass element N1 is an arithmetic logic.The source electrode of P pass element P1 is coupled to a voltage source V DD, and its drain electrode is coupled to the node 105 that a signal signal HI can be provided.The drain electrode of N pass element N1 is coupled to node 105, and its source electrode is coupled to the drain electrode of N pass element N2, and the source electrode of N pass element N2 is coupled to earth terminal.One clock signal clk inputs to the grid of P pass element P1 and N pass element N2 in a node 101.One data-signal DATA inputs to the grid of N pass element N1 via a node 103.Node 105 is coupled to the input end of one reverser/impact damper 107, and reverser/impact damper 107 has the node 109 that an output terminal is coupled to can provide an output signal OUT.One faint holding circuit 111 is coupled to node 105.This holding circuit 111 comprises one first reverser 111A, and its input end is coupled to node 105 with received signal signal HI, and its output terminal is coupled to the input end of one second reverser 111B, and the output terminal of this second reverser 111B is coupled to node 105.

Figure 1B is the clock figure of the running of explanation dynamic circuit 100, wherein, is that transverse axis is drawn clock signal clk, data-signal DATA, signal signal HI and output signal OUT with time.When the time when the T0 clock signal clk is low level, N pass element N2 closes and P pass element P1 opens, this can preliminary filling signal signal HI to logic high levle, to prepare coming operational data signal DATA in the rising edge of clock signal clk.In clock signal clk was cycle period semiperiod of low level, this output signal OUT was reversed device 107 and is pulled to low level.Because at the dynamic circuit shown in Figure 1A 100, typically can be configured to a series connection framework (the output signal OUT of front stage circuits being coupled to the data-signal DATA end of next stage circuit), therefore, as shown in time T 1, in clock signal clk was cycle period semiperiod of low level, data-signal DATA also typically was low level.So on time T 1, because data-signal DATA is a logic low level, then N pass element N1 closes.

At a later time T2, clock signal clk is pulled to high levle, N pass element N2 is opened, and P pass element P1 closes.Because data-signal DATA is a low level when time T 2, and N pass element N1 is a closing state, then makes signal signal HI can not be transfused to the end branch and drive.Yet during this section, holding circuit 111 is kept the accurate position of high logic of signal signal HI, and reverser 107 to keep output signal OUT be low level.During clock signal clk is the semiperiod of high levle, data-signal DATA is driven to the accurate position of a high logic, as shown in next time T 3, N pass element N1 also can open when N pass element N2 opened, this strength can be better than (overpower) holding circuit 111 and signal signal HI is discharged to the accurate position of a low logic, and reverser 107 meeting drive output respond the output signal of a high levle.

When time T 4, clock signal clk then transfers low level to and data-signal DATA also is driven to low level.Signal signal HI once more by P pass element P1 preliminary filling to high levle, and output signal OUT is pulled to low level.When next time T 5, when data-signal DATA was low level, clock signal clk was drawn to be high levle once more, made N pass element N2 open but N pass element N1 closes.Therefore, signal signal HI there is no and discharged and output signal OUT still keeps low level.Yet, being familiar with this operator can be learnt by a technology contents of the present invention, when driving data signal DATA is to high levle on time T 5 any points of back in cycle period semiperiod of clock signal clk, can causes signal signal HI discharge and cause output signal to be driven to low level.

Dynamic circuit 100 shown in Figure 1A comes soon (comprise static circuit and implement part (Static Implementation)) than other circuit framework with identity logic calculation function.Notice that when clock signal clk is low level signal signal HI can be that high levle makes that output signal OUT is a low level by preliminary filling by preliminary filling.(for example P pass element P1, N pass element N2) combines with arithmetic logic (for example N pass element N1) because the mechanism of clockization, so data-signal setting-up time (DATA setup time) in fact can be eliminated.Be familiar with this operator and can understand under the influence that is not unfavorable for the restriction of speed or related power, available more complex calculations logic (for example input multiplexer more than) replaces the simple calculations logic element N1 shown in dynamic circuit 100.

Though dynamic circuit is very quick, up to now dynamic circuit still can't provide locking mechanism to data-signal DATA or the provide mechanism of depositing of input to output signal.And mention indirectly as above-mentioned, during clock signal clk still is the semiperiod of high levle in, data-signal DATA transfers high levle to by low level, then output signal OUT can transfer high levle to by the low level of initial computing accordingly.This is why the logic pipeline deviser need provide the reason of depositing input for present dynamic circuit.

Fig. 2 A is the synoptic diagram according to a dynamic logic register 200 of one embodiment of the invention.The importation of dynamic logic register 200 comprises a P pass element P1 and N pass element N2, and it is similar to a complementary pair of the arithmetic unit in the dynamic circuit 100.The source electrode of P pass element P1 is coupled to voltage source V DD and its drain electrode is coupled to the precharged node 207 that a top signal TOP can be provided.Yet the N pass element N1 of dynamic circuit 100 is replaced by a dynamic evaluator 205.Dynamically evaluator 205 is coupled between the drain electrode of node 207 and N pass element N2, and the source electrode of N pass element N2 is coupled to earth terminal.Dynamically evaluator 205 can as N pass element N1 simply.At another and more in the complex embodiments, dynamically evaluator 205 is the structure of a more complicated computational logic, when it is high levle by clock signal clk, does " computing " for low level with top signal TOP is drop-down.In addition,, be familiar with this operator and can recognize, in this calculating process, can use any amount of data-signal although have only the computing of demonstration one single data-signal DATA.Dynamically evaluator 205 can be carried out the very simple extremely very complicated function of exclusive disjunction.

Clock signal clk inputs to the grid of P pass element P1 and N pass element N2, an input end of delayed backward logic 209 and the grid of a N pass element N5 via a node 201.Data-signal DATA inputs to the input end of a dynamic evaluator 205 via a node 203.Node 207 is coupled to the grid of a N pass element N6.The drain electrode of N pass element N6 is coupled to the source electrode of N pass element N5 and the source electrode of N pass element N6 is coupled to earth terminal.Circumscription logic (Qualifying Logic) 211 is coupled on the delayed backward logic 209, and it can be discussed following doing further.

Locking logic 213 comprises P pass element P2 and P3, N pass element N3, N4, N5 and N6 and adds logic (Additional Logic, AL) 215.The output terminal of delayed backward logic 209 is coupled to and a computing complete signal can be provided (wherein node 217 is coupled to the grid of P pass element P2, N pass element N3 and N4 for Evaluation complete signal, a node 217 EC).The source electrode of P pass element P2 is coupled to voltage source V DD.Node 207 is coupled to the source electrode of N passage transmitting element N3, the drain electrode of N passage transmitting element N3 be coupled to provide draw on one control signal PC one on draw Control Node 219.Node 219 is coupled to the drain electrode of P pass element P2 and the grid of P pass element P3.Adding logic 215 is coupled between the source electrode of voltage source V DD and P pass element P3.The drain electrode that the drain electrode of P pass element P3 is coupled to N pass element N4 is in output (or preparation output) node 221 that an output signal Q can be provided.The source electrode of N pass element N4 is coupled to the drain electrode of N pass element N5.Holding circuit 225 is coupled to node 221, wherein, holding circuit 225 comprises one first reverser 225A, and its input end is coupled to node 221 receiving the input end that output signal Q and its output terminal are coupled to one second reverser 225B, and the output terminal of the second reverser 225B is coupled to node 221.In one embodiment, holding circuit 225 with on draw the element P3 or the drop down element N4-N6 of storehouse to compare comparatively a relative weak holding circuit, holding circuit 225 can be subjected to drawing element P3 or the running of the drop down element N4-N6 of storehouse influence.

Node 221 is coupled to the input end of one reverser/impact damper 223, and its reverser/impact damper 223 has an output terminal to produce a reverse output signal QB.Because it is a weak relatively element to node 221 and reverser 225B that the P pass element P3 of storehouse and N pass element N4-N6 can manifest a tri-state state usually, therefore help input end or locking output signal that buffer output signal drives next logic.Reverser/impact damper 223 can be replaced to prevent logic reversal by one non-return (Non-Inverting) impact damper.Yet a non-return impact damper is implemented with the reverser of back-to-back (Back-to-Back) usually, may increase our undesired delay like this and can increase the time delay of clock to output.

Fig. 2 B is a clock figure (TimingDiagram) of the running of explanation dynamic logic register 200, wherein be transverse axis, draw the variation of clock signal clk, computing complete signal EC, data-signal DATA, top signal TOP, control signal PC, output signal Q and reverse output signal QB etc. with time.When the time was T0, when clock signal clk was low level, top signal TOP was the accurate position of a high logic by preliminary filling, the signal signal HI of top signal TOP this moment in the dynamic circuit 100.Computing complete signal EC is the form of a kind of delayed backward of clock signal clk.Yet before clock signal clk was low level, computing complete signal EC was a low level.Therefore, P pass element P2 for unlatching N pass element N3 and N4 for closing, and control signal PC is a high levle.After clock signal clk is driven to low level, computing complete signal EC is driven to high levle, therefore P pass element P2 is for closing N pass element N3 and N4 for opening, and therefore keeping control signal PC via N pass element N3 transmission top signal TOP is high levle.P pass element P3 and N pass element N5 provide a tri-state state for closing therefore at output signal Q, and it keeps its previous state by holding circuit 225.In the explanation of this embodiment, output signal Q is initially a high logic state in time T 0, and oppositely output signal QB is a low level.Data-signal DATA shows in addition is initially high levle.

One execution cycle starts from the rising edge of each clock signal clk, and next drop edge of ending at computing complete signal EC.Computing complete signal EC also can be considered to the revertive delay clock signal.Execution cycle is defined by the amount that delayed backward logic 209 postpones.Clock signal clk can rise when next time T 1, and this moment, P pass element P1 closed and N pass element N2 and N5 unlatching, initial by this one first execution cycle 231.During execution cycle, the state of top signal TOP is decided by dynamic evaluator 205 operational data signal DATA.In the explanation of the dynamic embodiment of evaluator 205, data-signal DATA is a high levle in time T 1, its can cause dynamic evaluator 205 during execution cycle in 231 computing top signal TOP is pulled down to low level thereby N pass element N6 is closed.Because computing complete signal EC still is a high levle in during execution cycle 231, so the state of top signal TOP can be passed to control signal PC via N passage transmitting element N3, and control signal PC is also drop-down to open P pass element P3 for low level.Suppose to add logic 215 during execution cycle in the source electrode of guiding voltage source V DD to P pass element P3, then output signal Q can by on draw for high levle (or maintaining high levle) and oppositely output signal QB can be pulled down to low level (or maintaining low level).

In the expiration of time T 2 delay periods, then computing complete signal EC can transfer low level to via delayed backward logic 209, thereby closes N pass element N3 and N4 and unlatching P pass element P2.When time T 2, when computing complete signal EC transferred low level to, then execution cycle 231 will finish.Any point after time T 2, data-signal DATA can change and not influence the reverse output signal QB of circuit 200.Therefore, when time T 2, control signal PC can be pulled to high levle via P pass element P2 by voltage source V DD once more, so P pass element P3 is closed.When clock signal clk is the half period circulation time of high levle, it is high levle that holding circuit 225 can be kept output signal Q, and reverser 223 can to keep reverse output signal QB be the logic low level.In order to illustrate, Fig. 2 B describes data-signal DATA when time T 3 be low level.Because N pass element N2 remains unlatching, the state of top signal TOP is uncertain or unknown temporarily, and it is with shadow region 233 expressions.And at the state of this section signal TOP in top in the time or real state by deciding forming of dynamic evaluator 205.When next time T 4, when next drop edge of clock signal clk took place, it can be closed N pass element N2 and P pass element P1 be opened, make top signal TOP once more via P pass element P1 by voltage source V DD preliminary filling to high levle.No matter how data-signal DATA from time T 3 to time T4 and top signal TOP change, because computing complete signal EC keeps low level, N pass element N3 and N4 be close and control signal PC be pulled to high levle and close P pass element P3, make the state of output signal Q and reverse output signal QB keep stable via holding circuit 225 and reverser 223 and do not change.

During time T 4, clock signal clk transfers low level to thereby closes N pass element N5.During time T 5, computing complete signal EC transfers high levle to and opens N pass element N3, makes the state of top signal TOP be passed to control signal PC via N passage transmitting element N3 once more, and its retentive control signal PC is high levle and P pass element P3 is closed.Though the state of N pass element N4 for opening, because N pass element N5 is what close, therefore, output signal Q and reverse output signal QB keep stable and do not change.

When time T 6, the operation that starts from next rising edge of clock signal clk comes down to identical.Yet in this situation, data-signal DATA is a high levle when the rising edge of a last clock signal clk, but almost is being pulled to high levle with the time for low level and with clock signal clk during in time T 6 at present.When computing complete signal EC transfers low level to, because data-signal DATA (from time T 6 to next time T 7) during second execution cycle 235 is a high levle, therefore data-signal DATA can be by dynamic evaluator 205 with the suitable computing of time enough, so output signal Q and reverse output signal QB signal can be set to suitable state.In the method, can recognize clock signal clk when initial execution cycle even be familiar with this operator, data-signal DATA transition under the time much at one, logic function still can be by the computing of success, so setting-up time is actually zero.

Operation during the 3rd execution cycle 237 also is similar, between next rising edge of the clock signal clk of the 3rd execution cycle 237 when time T 8 to next drop edge of the computing complete signal EC when time T 9.Yet in this situation, data-signal DATA is pulled to a logic low level, makes dynamic evaluator 205 can't carry out computing and top signal TOP maintains high levle, and it makes N pass element N6 open.Because computing complete signal EC still be high levle, be passed to control signal PC and keep P pass element P3 to close so N pass element N3 is the high levle state of unlatching and top signal TOP.During the 3rd execution cycle 237, clock signal clk is opened N pass element N5 and computing complete signal EC keeps the state of N pass element N4 for opening, therefore via N pass element N4, N5 and the N6 of storehouse, make output signal Q when being close to time T 8, be discharged to the accurate position of a low logic.Oppositely output signal QB is reversed device 223 and is set in high levle near time T 8 time.When computing complete signal EC transferred low level to during in time T 9, control signal PC was pulled to high levle (or maintaining high levle) via P pass element P2 by voltage source V DD, and N pass element N4 is closed.Therefore when 237 expirations of the 3rd execution cycle, P pass element P3 and N pass element N4 show that once more a tri-state state is to output signal Q.But,,, keep the state of output signal Q by holding circuit 225 as previous described one similar mode for remaining cycle period part.In the method, output signal Q and reverse output signal QB during execution cycle in signal can change, and after execution cycle expiration, keep stable status in the cycle period of clock signal clk.

Via locking logic 213, deposit action and finish at the execution cycle of the expiration when computing complete signal EC transfers low level to.Computing complete signal EC can close N pass element N3 and N4 and unlatching P pass element P2 when transferring low level to, it can be pulled to high levle with control signal PC and P pass element P3 is closed.Therefore, when clock signal clk is high levle, during first half clock cycle period, output signal Q can with on draw the drop down element N4-N6 of element P3 and storehouse to isolate.When clock signal clk transfers second half clock cycle period of low level to, N pass element N5 can close and computing complete signal EC still for low level, and P pass element P3 is still the state of closing so still keeping output signal Q (output signal Q still with on draw element and drop down element to isolate).Side by side, P pass element P1 opens and N pass element N2 closes, therefore, and can preliminary filling top signal TOP to logic high levle.Be accompanied by after the precharge of top signal TOP, computing complete signal EC can transfer high levle to, and it can be opened N pass element N3 and N4, therefore, allows the high levle state of signal TOP to keep the high levle of control signal PC.Precharge period expires when computing complete signal EC transfers high levle to can be opened N pass element N3, and therefore the high levle state transfer that allows top signal TOP makes P pass element P3 remain closing state to control signal PC.Therefore, whether the change of the data-signal DATA that no matter imports, and before beginning to next execution cycle from each execution cycle expiration back, the state of output signal Q and reverse output signal QB is kept by holding circuit 225.

Add logic 215 and can activate a function, this function can be reseted output signal Q or prevent that the logic high levle from appearring in output signal Q.Circumscription logic 211 is coupled to or is incorporated on the delayed backward logic 209, when clock signal clk transfers high levle to, can not make computing complete signal EC transfer high levle to effectively yet, therefore can prevent that on behalf of calculation function, top signal TOP from be passed to reverse output signal QB via N pass element N3.On the function, this makes the deviser be maintained the previous state of output signal Q and reverse output signal QB in when needed can be during next clock cycle period.

Add logic 215 and be of the present invention one important feature, itself and conventional dynamic circuit can add the function of more complexity by comparison to integrated circuit 200.P pass element P3 is configured to add a computing observer (Evaluate Strobe) of logic 215, and it is similar to the mode that dynamic evaluator 205 is provided the N pass element N of computing observation.Therefore, those who familiarize themselves with the technology can recognize when dynamic evaluator 205 during execution cycle during by computing, disclosed circuit 200 is also come computing to add logic 215 by favourable configuration during execution cycle according to the present invention.When control signal PC is low level, add logic 215 by computing (for example P pass element P3 is for opening).Therefore, adding logic 215 can use P logic (P pass element) to form whole independent and complicated function.The present invention not only provides the output of depositing of being carried out computing by dynamic evaluator 205, and also has by adding logic 215 to carry out the output of depositing of computing.

Being familiar with this operator, can to understand its advantage be to add logic 215 can implement with the P pass element of parallel connection, and its meaning is equal to dynamically to be implemented with the N pass element of series connection in the evaluator 205.Therefore, that then can implement complexity according to embodiments of the invention and or function (AND-OR Function) and can not produce the problem relevant, for example matrix effect (Body Effect) etc. with the storehouse series element.

Fig. 3 is the synoptic diagram of a simple and easy Fast Dynamic register 300, it is similar to dynamic logic register 200, wherein dynamic evaluation circuit 205 is replaced with single N pass element N1, delayed backward logic 209 is replaced by five reversers 301 of one group of series connection, and circumscription logic 211 and add logic 215 and be removed.What can recognize is, circumscription logic and/or add logic and can be added in this simple and easy quick logic register 300, and go up not significantly influence at setting-up time or data to the time of output (Data-to-Output).In a specific embodiment of the present invention, use the processing procedure of one 0.15 microns (Micron) to implement this simple and easy quick dynamic register 300, five reversers 301 of this series connection all can produce and be approximately 100 psec (Picoseconds, ps) a execution cycle, wherein, setting-up time be zero and clock to the reaction of output (Colck-to-Out) be approximately 60 psecs.

Fig. 4 is the process flow diagram of dynamically depositing an output signal method of explanation according to one embodiment of the invention.Begin operation by first block 401 as shown in Figure 4, wherein when a clock signal during in one first logic state, a first node is preset (Preset).For example in the foregoing embodiments, when clock signal clk was low level, node 207 meetings that top signal TOP then is provided were by the state of the accurate position of the paramount logic of preliminary filling.Operation continues to next block 403, and wherein when clock signal clk was converted to one second logic state, computing one function was to control the logic state of this first node.Continue previous example, when clock signal clk was set as high levle, dynamically evaluator 205 can come computing one logic function according to one or more input data signal.When top signal TOP was discharged to low level, this function can be by computing, otherwise when top signal TOP remained on high levle, this moment, function can be by computing.

In next block 405, clock signal is delayed and oppositely so that a delayed backward clock signal to be provided.For example, delayed backward logic 209 provides computing complete signal EC with delay clock signals CLK.Be to finish the function of wanting computing in order to minimum delay to be provided during disposing that this clock postpones in order to determine.In a synchronous line construction, a pipeline microprocessor or a fellow for example, the delay of its circuit at different levels may be different because of the function of circuit correspondences at different levels.Perhaps, in the circuit at different levels of series connection, general delay also can decide according to the minimum time of the logical operation of (Longest-Duration) between the most long-term in order to computing.This timing period is based upon an execution cycle, this execution cycle starts from the running transition (for example rising edge of clock signal) of clock signal, and ends at next transition (next drop edge of for example computing complete signal EC) of the correspondence of revertive delay clock signal.

In next block 407, the logic state of output node locks according to the logic state of the first node that is determined during execution cycle.With reference to dynamic logic register 200, when top signal TOP maintains high levle during execution cycle, output signal Q can be locked in low level, and when top signal TOP was pulled down to low level during execution cycle, output signal Q can be locked in high levle.In next block 409, the logic state of output node (for example output signal Q) remains unchanged between next execution cycle begins in each execution cycle expiration.In the method, in case logic state during each execution cycle by decision after, the state of output can be maintained to next execution cycle can not be subjected to input data signal with the integrality of determining output signal influence of change.In last block 411, the node of output is cushioned and is reverse to drive the input end of next stage.

Dynamic logic register according to an embodiment of the invention, it provides one can obviously reduce the speed of a dynamic circuit of retention time of input data and the structure of computing, and the characteristic that keeps the output data of a register.This dynamic logic register also shows a retention time that one zero setting-up times, are very short and a small clock to output time (Nominal Clock-to-Output Time), thus its speed can than lock is placed before the logic evaluator or structure afterwards also quick.The clock signal (for example computing complete signal EC) of one delay and reverse form is combined with a locking mechanism so that a quite short computing interval to be provided, wherein in this quite short computing at interval, dynamically the output (for example top signal TOP) of evaluator is allowed to be passed on the preparation output node (for example output signal Q).After this computing at interval, when the clock signal is cycle period semiperiod of high levle, output stack element (for example P pass element P3, N pass element N4, N5 and N6) is running together, when clock signal subsequently is between the semiperiod circulation of low level and high levle, and output stack element (for example P pass element P3, N pass element N4, N5 and N6) can show that a tri-state state prepare output node to this.One keeps the state that circuit maintains this preparation output node that presents in this computing at interval.One impact damper or reverser or its similar elements can drive an output signal according to this state for preparing output node.

The mechanism that a dynamic logic according to the present invention is deposited, the function that it can provide the locking input of complicated logical operation function and deposit output.In addition, because the present invention has removed the demand of setting-up time in the structure of locking-logic-locking (LATCH-LOGIC-LATCH), so data to the time response of exporting (Data-to-Output) significantly reduces.The mechanism that this dynamic logic is deposited is for also will simply providing the input end of locking and the output terminal of depositing to the complicated logical operation function fast than framework now.Highly be dependent on register and data be sent in the pipeline structure between circuit at different levels when being used in one, the disclosed a kind of dynamic register of the present invention it can make the running speed of single unit system significantly promote.

Though the present invention does detailed description with preferred embodiment, other preferred embodiment and be changed to may and expected.For example, dynamically evaluator design it according to the deviser can be simply or very complicated.Being familiar with present technique field person can recognize circumscription logic 211 and add logic 215 and can omit and need not or implement in any suitable manner.In addition, though the disclosed embodiment of the present invention utilizes the element of metal-oxide semiconductor (MOS) kenel, it has comprised complementary metal oxide semiconductor and similar elements such as NMOS and PMOS transistor etc., precisely because still can utilize the technology kenel and the framework of similar aspect or simulation to implement, for example dual-polarity elements or similar elements or the like.

At last, though the present invention is for realizing the optimal mode of purpose of the present invention, what only those who familiarize themselves with the technology should recognize is, it is not breaking away from following as defined spirit of the present invention of claim and scope, it can use disclosed idea and particular specific embodiment to be used as the basis immediately, carries out the design identical with purpose of the present invention or revises other structure.

Claims (16)

1. a dynamic logic register is characterized in that, comprises:

One complementary elements, required relatively a period of time the clock signal;

One dynamic evaluator, it is being coupled on precharged node between this complementary elements, and its data-signal according at least one input comes computing one function;

One delayed backward logic, it postpones and reverse form for one of this clock signal in order to receive this clock signal and to export a computing complete signal;

One locking logic, required relatively this clock signal, this computing complete signal and this precharged node, it is during the execution cycle between next edge of operation edge and this computing complete signal of this clock signal, control the state of an output node according to the state of this precharged node, otherwise, on this output node, present a tri-state state; And

One keeps circuit is coupled to this output node.

2. dynamic logic register as claimed in claim 1, wherein this complementary elements comprises:

One P pass element, its have a grid in order to receive this clock signal, a drain electrode is coupled to a voltage source and one source pole is coupled to this precharged node; And

One N pass element, its have a grid in order to receive this clock signal, a drain electrode is coupled to this dynamic evaluator and one source pole is coupled to earth terminal.

3. dynamic logic register as claimed in claim 1, wherein this delayed backward logic is selected from one of following: the reverser of at least one reverser, one group of series connection.

4. dynamic logic register as claimed in claim 1, further comprise a circumscription logic, this circumscription logic is coupled to this delayed backward logic and is used for operating to keep an original state of this output node, and further comprising one output buffer/reverser, this output buffer/reverser has that an input end is coupled to this output node and an output terminal is coupled to a reverse output node.

5. dynamic logic register as claimed in claim 1, wherein this locking logic comprises:

One N passage transmitting element, it has a grid and is coupled to this precharged node and one source pole and is coupled to and draws Control Node on one in order to receive this computing complete signal, a drain electrode;

Draw element on one the one P passage, it has a grid and is coupled to a voltage source and one source pole and is coupled to and draws Control Node on this in order to receive this computing complete signal, a drain electrode;

Draw element on one the 2nd P passage, it has a grid and is coupled to and draws Control Node, a drain electrode to be coupled to this voltage source and one source pole is coupled to this output node on this; And

A plurality of N passage drop down element, it is coupled between this output node and the earth terminal, and by this computing complete signal, this clock signal and the control of this precharged node.

6. dynamic logic register as claimed in claim 5, wherein these a plurality of N passage drop down element comprise:

One the one N passage drop down element, its have a grid in order to receive this computing complete signal, a drain electrode is coupled to this output node and one source pole;

One the 2nd N passage drop down element, its have a grid in order to receive this clock signal, a drain electrode is coupled to this source electrode and the one source pole of a N passage drop down element; And

One the 3rd N passage drop down element, it has a grid and is coupled to this source electrode and the one source pole that this precharged node, a drain electrode be coupled to the 2nd N passage drop down element and is coupled to earth terminal.

7. dynamic logic register as claimed in claim 5 further comprises one and adds logic element, and this adds logic element and is coupled on this voltage source and the 2nd P passage and draws between the element, and it is used for controlling a particular state of this output node output.

8. a dynamic lock-in circuit is characterized in that, comprises:

One dynamic circuit, when it is low level when a clock circuit, preliminary filling one first node, and when this clock signal transfers high levle to, calculate a function to control the state of this first node;

One delayed backward device is in order to receive this clock signal, so that a revertive delay clock signal to be provided;

One lock-in circuit, it is coupled on this dynamic circuit and this delayed backward device, this lock-in circuit during an execution cycle in, control the state of an output node according to the state of this first node, otherwise, present a three-state to this output node, wherein this execution cycle is to start from when this clock signal transfers high levle to and end to transfer low level to when this revertive delay clock signal next time; And

One keeps circuit, and it is coupled on this output node.

9. dynamic lock-in circuit as claimed in claim 8, wherein this dynamic lock-in circuit comprises:

One P pass element, it is coupled on this first node, when this clock signal is low level, this first node of its preliminary filling;

One logical circuit, it is coupled on this first node, this function of its computing; And

One N pass element, it is coupled on this logical circuit, and when this clock signal transferred high levle to, it can make this this function of logical circuit computing.

10. dynamic lock-in circuit as claimed in claim 8, wherein this delayed backward device comprises the reverser of one group of series connection.

11. dynamic lock-in circuit as claimed in claim 8, wherein this lock-in circuit comprises:

One N pass element, when this revertive delay clock signal was high levle, this N pass element was coupled to a Section Point to this first node;

One P pass element, when this revertive delay clock signal was low level, this P pass element was pulled to high levle with this Section Point; And

One storehouse element, it is coupled to this output node, this stack element comprises draws element and a plurality of pull device on one, when this Section Point is low level, draw element to be used for this output node is pulled to high levle on being somebody's turn to do, and during this execution cycle, when this first node was high levle, these a plurality of pull devices were pulled to low level with this output node.

12. dynamic lock-in circuit as claimed in claim 8, further comprise the circumscription logic element, this circumscription logic element is coupled on this delayed backward device, and what provide in this lock-in circuit one adds logic element and export a predetermined logic state in order to control this output node.

13. a method of dynamically depositing an output signal comprises:

When a clock signal is preset a first node in one first logic state;

When this clock signal changed one second logic state into, dynamically computing one function was in order to control the state of this first node;

Postpone to reach reverse this clock signal so that a delayed backward clock signal to be provided;

Lock a logic state of an output node according to this logic state of this first node that is determined in during an execution cycle, wherein this execution cycle starts from changing this second logic state into when this clock signal, and ends at the conversion when next correspondence of this delayed backward clock signal; And

Between each execution cycle, keep this logic state of this output node.

14. method of dynamically depositing an output signal as claimed in claim 13, wherein should comprise this first node to one high logic state of preliminary filling by default first node, and wherein this this logic state of keeping this output node comprises and presents a tri-state state to this output node and couple one and keep circuit to this output node.

15. method of dynamically depositing an output signal as claimed in claim 13 more comprises buffering and reverse this output node.

16. method of dynamically depositing an output signal as claimed in claim 13, this first logic state are that a low logic state and this second logic state are a high logic state, wherein should the locking one output node a logic state, comprise:

When this delayed backward clock signal is a high logic state, transmits on the logic state to of this first node and draw Control Node;

When this delayed backward clock signal during at a low logic state, should on draw Control Node to be pulled to a high logic state;

When drawing Control Node on this, this output node is pulled to a high logic state at low logic state; And

When in this first node is during an execution cycle, being a high logic state, this output node is pulled to a low logic state.

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