TW200731670A - Inverting dynamic register with data-dependent hold time reduction mechanism - Google Patents

Abstract

A dynamic logic register including evaluation logic, delay logic, and latching logic. The evaluation logic evaluates a logic function based on data input. The logic function evaluates to either a first state or a second state. The delay logic generates a kill signal, where the kill signal is a delayed version of a clock signal, and where the delay between the clock and the kill signals comprises a hold time, and where the hold time is shorted when the logic function evaluates to the first state. The latching logic is responsive to the clock and the kill signals and the state of pre-charged node, and controls the state of an output node based on the state of a pre-charged node during an evaluation period between an operative edge of the clock signal and next edge of the kill signal, and otherwise presents a tri-state condition to said output node.