DE60143981D1 - Substratstruktur - Google Patents

Substratstruktur

Info

Publication number
DE60143981D1
DE60143981D1 DE60143981T DE60143981T DE60143981D1 DE 60143981 D1 DE60143981 D1 DE 60143981D1 DE 60143981 T DE60143981 T DE 60143981T DE 60143981 T DE60143981 T DE 60143981T DE 60143981 D1 DE60143981 D1 DE 60143981D1
Authority
DE
Germany
Prior art keywords
substrate structure
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60143981T
Other languages
English (en)
Inventor
Hideaki Kaino
Hiromichi Watanabe
Shinichi Sugiura
Shuji Kimura
Shigeru Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Ten Ltd
Original Assignee
Denso Ten Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Ten Ltd filed Critical Denso Ten Ltd
Application granted granted Critical
Publication of DE60143981D1 publication Critical patent/DE60143981D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09436—Pads or lands on permanent coating which covers the other conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
DE60143981T 2000-11-27 2001-11-27 Substratstruktur Expired - Lifetime DE60143981D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000358903A JP3857042B2 (ja) 2000-11-27 2000-11-27 基板構造

Publications (1)

Publication Number Publication Date
DE60143981D1 true DE60143981D1 (de) 2011-03-17

Family

ID=18830736

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60143981T Expired - Lifetime DE60143981D1 (de) 2000-11-27 2001-11-27 Substratstruktur

Country Status (5)

Country Link
US (1) US6750537B2 (de)
EP (1) EP1209957B1 (de)
JP (1) JP3857042B2 (de)
CN (1) CN1190114C (de)
DE (1) DE60143981D1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012142371A (ja) * 2010-12-28 2012-07-26 Mitsubishi Electric Corp 半導体パッケージ
JP2023043862A (ja) * 2021-09-16 2023-03-29 方略電子股▲ふん▼有限公司 電子装置

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3639443A1 (de) * 1986-11-18 1988-05-26 Ant Nachrichtentech Leiterplatte und verfahren zu deren herstellung
GB8705543D0 (en) * 1987-03-10 1987-04-15 Int Computers Ltd Printed circuit board
US4967314A (en) 1988-03-28 1990-10-30 Prime Computer Inc. Circuit board construction
JPH0499394A (ja) * 1990-08-17 1992-03-31 Cmk Corp 多層プリント配線板
JPH05218618A (ja) * 1992-01-30 1993-08-27 Cmk Corp プリント配線板の製造方法
JP2721093B2 (ja) * 1992-07-21 1998-03-04 三菱電機株式会社 半導体装置
US5371403A (en) * 1993-09-24 1994-12-06 Vlsi Technology, Inc. High performance package using high dielectric constant materials for power/ground and low dielectric constant materials for signal lines
JPH08116174A (ja) * 1994-08-25 1996-05-07 Matsushita Electric Ind Co Ltd 回路形成基板およびその製造方法
US5509200A (en) 1994-11-21 1996-04-23 International Business Machines Corporation Method of making laminar stackable circuit board structure
US5672911A (en) * 1996-05-30 1997-09-30 Lsi Logic Corporation Apparatus to decouple core circuits power supply from input-output circuits power supply in a semiconductor device package
US5708296A (en) * 1996-06-24 1998-01-13 Intel Corporation Power-ground plane for a C4 flip-chip substrate
DE19642929A1 (de) * 1996-10-17 1997-07-17 Siemens Ag Kontaktierung wenigstens eines Bauelementes auf einer mehrlagigen Leiterplatte
TW424321B (en) * 1996-10-31 2001-03-01 Sharp Kk Integrated electronic circuit
JPH10284838A (ja) 1997-04-01 1998-10-23 Murata Mfg Co Ltd 多層回路基板及びその実装方法
US5847936A (en) * 1997-06-20 1998-12-08 Sun Microsystems, Inc. Optimized routing scheme for an integrated circuit/printed circuit board
JP4099837B2 (ja) 1997-08-27 2008-06-11 株式会社村田製作所 低温焼成セラミック多層基板の製造方法
EP1895589A3 (de) * 1997-10-17 2013-04-03 Ibiden Co., Ltd. Substrat für eine Halbleiterpackung
WO1999034654A1 (fr) * 1997-12-29 1999-07-08 Ibiden Co., Ltd. Plaquette a circuits imprimes multicouche
US5898217A (en) * 1998-01-05 1999-04-27 Motorola, Inc. Semiconductor device including a substrate having clustered interconnects
US6064113A (en) * 1998-01-13 2000-05-16 Lsi Logic Corporation Semiconductor device package including a substrate having bonding fingers within an electrically conductive ring surrounding a die area and a combined power and ground plane to stabilize signal path impedances
US6008534A (en) * 1998-01-14 1999-12-28 Lsi Logic Corporation Integrated circuit package having signal traces interposed between power and ground conductors in order to form stripline transmission lines
US6187652B1 (en) * 1998-09-14 2001-02-13 Fujitsu Limited Method of fabrication of multiple-layer high density substrate
JP2000100985A (ja) * 1998-09-17 2000-04-07 Nitto Denko Corp 半導体素子実装用基板およびその製造方法と用途
US6239485B1 (en) * 1998-11-13 2001-05-29 Fujitsu Limited Reduced cross-talk noise high density signal interposer with power and ground wrap
US6413620B1 (en) * 1999-06-30 2002-07-02 Kyocera Corporation Ceramic wiring substrate and method of producing the same
US6137161A (en) * 1999-09-14 2000-10-24 International Business Machines Corporation Interposer array module for capacitive decoupling and filtering
JP2001168125A (ja) * 1999-12-03 2001-06-22 Nec Corp 半導体装置
US6388207B1 (en) * 2000-12-29 2002-05-14 Intel Corporation Electronic assembly with trench structures and methods of manufacture

Also Published As

Publication number Publication date
EP1209957A2 (de) 2002-05-29
EP1209957B1 (de) 2011-02-02
JP3857042B2 (ja) 2006-12-13
US6750537B2 (en) 2004-06-15
CN1190114C (zh) 2005-02-16
EP1209957A3 (de) 2003-07-23
US20020063325A1 (en) 2002-05-30
CN1356862A (zh) 2002-07-03
JP2002164666A (ja) 2002-06-07

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