DE60136007D1 - Verfahren zur herstellung einer stapelstruktur - Google Patents

Verfahren zur herstellung einer stapelstruktur

Info

Publication number
DE60136007D1
DE60136007D1 DE60136007T DE60136007T DE60136007D1 DE 60136007 D1 DE60136007 D1 DE 60136007D1 DE 60136007 T DE60136007 T DE 60136007T DE 60136007 T DE60136007 T DE 60136007T DE 60136007 D1 DE60136007 D1 DE 60136007D1
Authority
DE
Germany
Prior art keywords
crystalline
tilt angle
structures
face
producing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60136007T
Other languages
English (en)
Inventor
Franck Fournel
Hubert Moriceau
Marc Zussy
Noel Magnea
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Application granted granted Critical
Publication of DE60136007D1 publication Critical patent/DE60136007D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Micromachines (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Fuel Cell (AREA)
  • Turbine Rotor Nozzle Sealing (AREA)
  • Seeds, Soups, And Other Foods (AREA)
  • Manipulator (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Optical Integrated Circuits (AREA)
DE60136007T 2000-12-28 2001-12-27 Verfahren zur herstellung einer stapelstruktur Expired - Lifetime DE60136007D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0017215A FR2819099B1 (fr) 2000-12-28 2000-12-28 Procede de realisation d'une structure empilee
PCT/FR2001/004130 WO2002054466A1 (fr) 2000-12-28 2001-12-27 Procede de realisation d'une structure empilee

Publications (1)

Publication Number Publication Date
DE60136007D1 true DE60136007D1 (de) 2008-11-13

Family

ID=8858336

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60136007T Expired - Lifetime DE60136007D1 (de) 2000-12-28 2001-12-27 Verfahren zur herstellung einer stapelstruktur

Country Status (7)

Country Link
US (1) US7229897B2 (de)
EP (1) EP1346402B1 (de)
JP (1) JP4167065B2 (de)
AT (1) ATE409955T1 (de)
DE (1) DE60136007D1 (de)
FR (1) FR2819099B1 (de)
WO (1) WO2002054466A1 (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
FR2848336B1 (fr) 2002-12-09 2005-10-28 Commissariat Energie Atomique Procede de realisation d'une structure contrainte destinee a etre dissociee
FR2850487B1 (fr) * 2002-12-24 2005-12-09 Commissariat Energie Atomique Procede de realisation de substrats mixtes et structure ainsi obtenue
FR2856844B1 (fr) 2003-06-24 2006-02-17 Commissariat Energie Atomique Circuit integre sur puce de hautes performances
FR2857953B1 (fr) 2003-07-21 2006-01-13 Commissariat Energie Atomique Structure empilee, et procede pour la fabriquer
FR2861497B1 (fr) 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
JP2005279843A (ja) * 2004-03-29 2005-10-13 Univ Of Tokyo 細線を含む結晶材料とその製造方法、およびこれを用いたナノ細線デバイス
FR2876498B1 (fr) 2004-10-12 2008-03-14 Commissariat Energie Atomique Procede de realisation d'heterostructures resonnantes a transport planaire
FR2877662B1 (fr) 2004-11-09 2007-03-02 Commissariat Energie Atomique Reseau de particules et procede de realisation d'un tel reseau.
US7422956B2 (en) 2004-12-08 2008-09-09 Advanced Micro Devices, Inc. Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers
FR2889887B1 (fr) 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
FR2891281B1 (fr) 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
FR2895391B1 (fr) * 2005-12-27 2008-01-25 Commissariat Energie Atomique Procede d'elaboration de nanostructures ordonnees
FR2895419B1 (fr) * 2005-12-27 2008-02-22 Commissariat Energie Atomique Procede de realisation simplifiee d'une structure epitaxiee
FR2895571B1 (fr) * 2005-12-28 2008-04-18 Commissariat Energie Atomique Procede de realisation d'une jonction pn electroluminescente en materiau semi-conducteur par collage moleculaire
FR2903810B1 (fr) 2006-07-13 2008-10-10 Commissariat Energie Atomique Procede de nanostructuration de la surface d'un substrat
JP2008060355A (ja) * 2006-08-31 2008-03-13 Sumco Corp 貼り合わせウェーハの製造方法および貼り合わせウェーハ
FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
FR2925221B1 (fr) 2007-12-17 2010-02-19 Commissariat Energie Atomique Procede de transfert d'une couche mince
US8129256B2 (en) * 2008-08-19 2012-03-06 International Business Machines Corporation 3D integrated circuit device fabrication with precisely controllable substrate removal
FR2937797B1 (fr) * 2008-10-28 2010-12-24 S O I Tec Silicon On Insulator Tech Procede de fabrication et de traitement d'une structure de type semi-conducteur sur isolant, permettant de deplacer des dislocations, et structure correspondante
FR2942674B1 (fr) * 2009-02-27 2011-12-16 Commissariat Energie Atomique Procede d'elaboration d'un substrat hybride par recristallisation partielle d'une couche mixte
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
US8367519B2 (en) * 2009-12-30 2013-02-05 Memc Electronic Materials, Inc. Method for the preparation of a multi-layered crystalline structure
FR2975109B1 (fr) 2011-05-13 2013-07-05 Commissariat Energie Atomique Procede de realisation d'une structure a reseau bidimensionnel de dislocations coin a periode maitrisee
JP2013001624A (ja) * 2011-06-21 2013-01-07 Sumitomo Electric Ind Ltd Ｉｉｉ族窒化物複合基板およびその評価方法
SG186759A1 (en) * 2012-01-23 2013-02-28 Ev Group E Thallner Gmbh Method and device for permanent bonding of wafers, as well as cutting tool
FR3039699B1 (fr) 2015-07-31 2017-07-28 Commissariat Energie Atomique Procede de realisation d'un dispositif electronique
FR3109016B1 (fr) * 2020-04-01 2023-12-01 Soitec Silicon On Insulator Structure demontable et procede de transfert d’une couche mettant en œuvre ladite structure demontable

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69127582T2 (de) * 1990-05-18 1998-03-26 Fujitsu Ltd Verfahren zur Herstellung eines Halbleitersubstrates und Verfahren zur Herstellung einer Halbleiteranordnung unter Verwendung dieses Substrates
JPH04226031A (ja) * 1990-05-18 1992-08-14 Fujitsu Ltd 半導体ウエハの製造方法および該ウエハから成る半導体装置の製造方法
JPH05109594A (ja) * 1991-10-18 1993-04-30 Hitachi Ltd 半導体基板、その製造方法および半導体装置
JPH05251294A (ja) * 1992-03-06 1993-09-28 Iwao Matsunaga ガリウム化合物半導体単結晶ウエハ及びその製造方法
TW289837B (de) * 1994-01-18 1996-11-01 Hwelett Packard Co
JPH07335511A (ja) * 1994-06-13 1995-12-22 Nippon Telegr & Teleph Corp <Ntt> 張り合わせウエハ
JP2820120B2 (ja) * 1996-06-03 1998-11-05 日本電気株式会社 半導体基板の製造方法
US5783477A (en) * 1996-09-20 1998-07-21 Hewlett-Packard Company Method for bonding compounds semiconductor wafers to create an ohmic interface
EP0995227A4 (de) * 1997-05-12 2000-07-05 Silicon Genesis Corp Kontrolliertes spaltungsverfahren
US6013563A (en) * 1997-05-12 2000-01-11 Silicon Genesis Corporation Controlled cleaning process
JPH1140786A (ja) * 1997-07-18 1999-02-12 Denso Corp 半導体基板及びその製造方法
FR2766620B1 (fr) * 1997-07-22 2000-12-01 Commissariat Energie Atomique Realisation de microstructures ou de nanostructures sur un support
JP3452122B2 (ja) * 1998-04-22 2003-09-29 三菱住友シリコン株式会社 Ｓｏｉ基板の製造方法

Also Published As

Publication number Publication date
EP1346402B1 (de) 2008-10-01
EP1346402A1 (de) 2003-09-24
US20050101095A1 (en) 2005-05-12
WO2002054466A1 (fr) 2002-07-11
JP2004522296A (ja) 2004-07-22
FR2819099B1 (fr) 2003-09-26
FR2819099A1 (fr) 2002-07-05
JP4167065B2 (ja) 2008-10-15
ATE409955T1 (de) 2008-10-15
US7229897B2 (en) 2007-06-12

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Legal Events

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8364 No opposition during term of opposition