DE60130933D1 - System und verfahren mit geringerer systembelastung zur prüfung der grenzüberschreitung von java arrays - Google Patents

System und verfahren mit geringerer systembelastung zur prüfung der grenzüberschreitung von java arrays

Info

Publication number
DE60130933D1
DE60130933D1 DE60130933T DE60130933T DE60130933D1 DE 60130933 D1 DE60130933 D1 DE 60130933D1 DE 60130933 T DE60130933 T DE 60130933T DE 60130933 T DE60130933 T DE 60130933T DE 60130933 D1 DE60130933 D1 DE 60130933D1
Authority
DE
Germany
Prior art keywords
array
access command
current
during
machine cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60130933T
Other languages
English (en)
Other versions
DE60130933T2 (de
Inventor
Lonnie Goff
David Evoy
Menno Lindwer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of DE60130933D1 publication Critical patent/DE60130933D1/de
Application granted granted Critical
Publication of DE60130933T2 publication Critical patent/DE60130933T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44589—Program code verification, e.g. Java bytecode verification, proof-carrying code

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
  • Devices For Executing Special Programs (AREA)
DE60130933T 2000-09-26 2001-09-21 System und verfahren mit geringerer systembelastung zur prüfung der grenzüberschreitung von java arrays Expired - Lifetime DE60130933T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US670496 1996-06-27
US09/670,496 US6782407B1 (en) 2000-09-26 2000-09-26 System and method for low overhead boundary checking of java arrays
PCT/EP2001/010990 WO2002027488A2 (en) 2000-09-26 2001-09-21 System and method for low overhead boundary checking of java arrays

Publications (2)

Publication Number Publication Date
DE60130933D1 true DE60130933D1 (de) 2007-11-22
DE60130933T2 DE60130933T2 (de) 2008-02-07

Family

ID=24690621

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60130933T Expired - Lifetime DE60130933T2 (de) 2000-09-26 2001-09-21 System und verfahren mit geringerer systembelastung zur prüfung der grenzüberschreitung von java arrays

Country Status (7)

Country Link
US (1) US6782407B1 (de)
EP (1) EP1451681B1 (de)
JP (1) JP2004510249A (de)
KR (1) KR100802686B1 (de)
AT (1) ATE375550T1 (de)
DE (1) DE60130933T2 (de)
WO (1) WO2002027488A2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9207958B1 (en) 2002-08-12 2015-12-08 Arm Finance Overseas Limited Virtual machine coprocessor for accelerating software execution
US7752424B2 (en) * 2007-08-08 2010-07-06 Arm Limited Null value checking instruction

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3401376A (en) * 1965-11-26 1968-09-10 Burroughs Corp Central processor
EP0540155A3 (en) 1991-10-29 1993-07-21 Advanced Micro Devices, Inc. Digital limit checking system
US6026484A (en) 1993-11-30 2000-02-15 Texas Instruments Incorporated Data processing apparatus, system and method for if, then, else operation using write priority
US6116768A (en) 1993-11-30 2000-09-12 Texas Instruments Incorporated Three input arithmetic logic unit with barrel rotator
US5983340A (en) 1995-12-07 1999-11-09 Conexant Systems, Inc. Microprocessor system with flexible instruction controlled by prior instruction
WO1997027536A1 (en) 1996-01-24 1997-07-31 Sun Microsystems, Inc. Instruction folding for a stack-based machine
KR100466722B1 (ko) 1996-01-24 2005-04-14 선 마이크로시스템즈 인코퍼레이티드 어레이경계검사방법및장치와,이를포함하는컴퓨터시스템
US5991863A (en) 1996-08-30 1999-11-23 Texas Instruments Incorporated Single carry/borrow propagate adder/decrementer for generating register stack addresses in a microprocessor
US6009505A (en) 1996-12-02 1999-12-28 Compaq Computer Corp. System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot

Also Published As

Publication number Publication date
WO2002027488A2 (en) 2002-04-04
EP1451681B1 (de) 2007-10-10
KR20020087389A (ko) 2002-11-22
US6782407B1 (en) 2004-08-24
EP1451681A2 (de) 2004-09-01
DE60130933T2 (de) 2008-02-07
ATE375550T1 (de) 2007-10-15
WO2002027488A3 (en) 2004-06-10
JP2004510249A (ja) 2004-04-02
KR100802686B1 (ko) 2008-02-12

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