BR9808156A - Memória de dados - Google Patents

Memória de dados

Info

Publication number
BR9808156A
BR9808156A BR9808156-0A BR9808156A BR9808156A BR 9808156 A BR9808156 A BR 9808156A BR 9808156 A BR9808156 A BR 9808156A BR 9808156 A BR9808156 A BR 9808156A
Authority
BR
Brazil
Prior art keywords
memory
redundancy
allocation
memory cell
memory cells
Prior art date
Application number
BR9808156-0A
Other languages
English (en)
Inventor
Thomas Zettler
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of BR9808156A publication Critical patent/BR9808156A/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/802—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout by encoding redundancy signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

Patente de Invenção:<B>"MEMóRIA DE DADOS"<D>. A invenção refere-se a uma memória de dados que apresenta as seguintes características: -pelo menos um campo de células de memória, que apresenta células de memória; -um circuito de redundância, que apresenta pelo menos uma célula de memória de redundância; -um circuito de seleção de linhas seletivas-redundância, que apresenta pelo menos uma memória de conjugação na qual é amazenável uma informação de conjugação e onde, com base na informação de conjugação, pelo menos uma célula de memória de redundância é conjugável a pelo menos uma célula de memória; -a memória de conjugação apresenta uma célula de memória de conjugação com uma intermediária para a recepção de informação de conjugação. Nas memórias de dados conhecidas são requeridos, de acordo com o processo de programação empregado, tempos de programação relativamente longos na conjugação de células de memórias de redundância às células de memória. Nas memórias de dados de acordo com a invenção a informação de conjugação de memória intermediária é transmissível de mamória intermediária para a célula de memória de conjugação. Com isso, é possível conjugar as células de memória de redundância com rapidez e com pequeno dispêndio de energia às células de memória defeituosas.
BR9808156-0A 1997-03-05 1998-01-30 Memória de dados BR9808156A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19708965A DE19708965C2 (de) 1997-03-05 1997-03-05 Halbleiterdatenspeicher
PCT/DE1998/000274 WO1998039708A1 (de) 1997-03-05 1998-01-30 Datenspeicher mit einer redundanzschaltung

Publications (1)

Publication Number Publication Date
BR9808156A true BR9808156A (pt) 2000-03-28

Family

ID=7822313

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9808156-0A BR9808156A (pt) 1997-03-05 1998-01-30 Memória de dados

Country Status (9)

Country Link
EP (1) EP0965083B1 (pt)
JP (1) JP2000509880A (pt)
KR (1) KR20000075920A (pt)
CN (1) CN1249828A (pt)
AT (1) ATE202861T1 (pt)
BR (1) BR9808156A (pt)
DE (2) DE19708965C2 (pt)
ES (1) ES2161043T3 (pt)
WO (1) WO1998039708A1 (pt)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU3073800A (en) * 1999-02-01 2000-08-25 Hitachi Limited Semiconductor integrated circuit and nonvolatile memory element
DE10063627B4 (de) 2000-12-20 2016-03-31 Polaris Innovations Ltd. Integrierte Schaltung mit einer Datenverarbeitungseinheit und einem Zwischenspeicher
DE10233910B4 (de) 2002-07-25 2004-07-15 Infineon Technologies Ag Schaltungsanordnung zum Auslesen einer programmierbaren Verbindung
US7505319B2 (en) * 2007-01-31 2009-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for high efficiency redundancy scheme for multi-segment SRAM

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4376300A (en) * 1981-01-02 1983-03-08 Intel Corporation Memory system employing mostly good memories
US5153880A (en) * 1990-03-12 1992-10-06 Xicor, Inc. Field-programmable redundancy apparatus for memory arrays
US5200922A (en) * 1990-10-24 1993-04-06 Rao Kameswara K Redundancy circuit for high speed EPROM and flash memory devices
US5357463A (en) * 1992-11-17 1994-10-18 Micron Semiconductor, Inc. Method for reverse programming of a flash EEPROM

Also Published As

Publication number Publication date
CN1249828A (zh) 2000-04-05
DE19708965C2 (de) 1999-06-10
WO1998039708A1 (de) 1998-09-11
EP0965083A1 (de) 1999-12-22
DE19708965A1 (de) 1998-09-24
DE59800964D1 (de) 2001-08-09
ES2161043T3 (es) 2001-11-16
JP2000509880A (ja) 2000-08-02
KR20000075920A (ko) 2000-12-26
EP0965083B1 (de) 2001-07-04
ATE202861T1 (de) 2001-07-15

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Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 6A,7A,8A E 9A ANUIDADES.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 1892 DE 10/04/2007.