DE60127520D1 - Prozessor mit Befehlscache mit niedrigem Stromverbrauch - Google Patents
Prozessor mit Befehlscache mit niedrigem StromverbrauchInfo
- Publication number
- DE60127520D1 DE60127520D1 DE60127520T DE60127520T DE60127520D1 DE 60127520 D1 DE60127520 D1 DE 60127520D1 DE 60127520 T DE60127520 T DE 60127520T DE 60127520 T DE60127520 T DE 60127520T DE 60127520 D1 DE60127520 D1 DE 60127520D1
- Authority
- DE
- Germany
- Prior art keywords
- processor
- low power
- power command
- command cache
- cache
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0882—Page mode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1028—Power efficiency
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000391369A JP2002196981A (ja) | 2000-12-22 | 2000-12-22 | データ処理装置 |
JP2000391369 | 2000-12-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60127520D1 true DE60127520D1 (de) | 2007-05-10 |
DE60127520T2 DE60127520T2 (de) | 2007-09-06 |
Family
ID=18857521
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60127520T Expired - Fee Related DE60127520T2 (de) | 2000-12-22 | 2001-12-21 | Prozessor mit Befehlscache mit niedrigem Stromverbrauch |
Country Status (7)
Country | Link |
---|---|
US (1) | US6760810B2 (de) |
EP (1) | EP1217502B1 (de) |
JP (1) | JP2002196981A (de) |
KR (1) | KR100758185B1 (de) |
CN (1) | CN1155893C (de) |
DE (1) | DE60127520T2 (de) |
TW (1) | TW581966B (de) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7330954B2 (en) * | 2002-04-18 | 2008-02-12 | Intel Corporation | Storing information in one of at least two storage devices based on a storage parameter and an attribute of the storage devices |
JP2004171177A (ja) * | 2002-11-19 | 2004-06-17 | Renesas Technology Corp | キャッシュシステムおよびキャッシュメモリ制御装置 |
US7263621B2 (en) * | 2004-11-15 | 2007-08-28 | Via Technologies, Inc. | System for reducing power consumption in a microprocessor having multiple instruction decoders that are coupled to selectors receiving their own output as feedback |
TW200821831A (en) * | 2005-12-21 | 2008-05-16 | Nxp Bv | Schedule based cache/memory power minimization technique |
JP4980751B2 (ja) | 2007-03-02 | 2012-07-18 | 富士通セミコンダクター株式会社 | データ処理装置、およびメモリのリードアクティブ制御方法。 |
JP4354001B1 (ja) | 2008-07-03 | 2009-10-28 | Necエレクトロニクス株式会社 | メモリ制御回路および集積回路 |
US8200999B2 (en) | 2008-08-11 | 2012-06-12 | International Business Machines Corporation | Selective power reduction of memory hardware |
JP5793061B2 (ja) * | 2011-11-02 | 2015-10-14 | ルネサスエレクトロニクス株式会社 | キャッシュメモリ装置、キャッシュ制御方法、およびマイクロプロセッサシステム |
US8503264B1 (en) | 2011-11-18 | 2013-08-06 | Xilinx, Inc. | Reducing power consumption in a segmented memory |
US9396117B2 (en) * | 2012-01-09 | 2016-07-19 | Nvidia Corporation | Instruction cache power reduction |
US9552032B2 (en) | 2012-04-27 | 2017-01-24 | Nvidia Corporation | Branch prediction power reduction |
US9547358B2 (en) | 2012-04-27 | 2017-01-17 | Nvidia Corporation | Branch prediction power reduction |
US8743653B1 (en) | 2012-06-20 | 2014-06-03 | Xilinx, Inc. | Reducing dynamic power consumption of a memory circuit |
CN104050092B (zh) | 2013-03-15 | 2018-05-01 | 上海芯豪微电子有限公司 | 一种数据缓存系统及方法 |
US10860495B2 (en) * | 2016-11-29 | 2020-12-08 | Arm Limited | Storage circuitry responsive to a tag-matching command |
CN113138657A (zh) * | 2020-01-17 | 2021-07-20 | 炬芯科技股份有限公司 | 一种降低cache访问功耗的方法和电路 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01154261A (ja) * | 1987-12-11 | 1989-06-16 | Toshiba Corp | 情報処理装置 |
JPH0786847B2 (ja) * | 1988-08-09 | 1995-09-20 | 松下電器産業株式会社 | キャッシュメモリ |
JPH04328656A (ja) * | 1991-04-30 | 1992-11-17 | Toshiba Corp | キャッシュメモリ |
US5913223A (en) * | 1993-01-25 | 1999-06-15 | Sheppard; Douglas Parks | Low power set associative cache memory |
JP3589485B2 (ja) | 1994-06-07 | 2004-11-17 | 株式会社ルネサステクノロジ | セットアソシアティブ方式のメモリ装置およびプロセッサ |
JPH08263370A (ja) * | 1995-03-27 | 1996-10-11 | Toshiba Microelectron Corp | キャッシュメモリシステム |
US5724611A (en) * | 1996-04-25 | 1998-03-03 | Vlsi Technology, Inc. | Automatic cache controller system and method therefor |
US5911153A (en) * | 1996-10-03 | 1999-06-08 | International Business Machines Corporation | Memory design which facilitates incremental fetch and store requests off applied base address requests |
US5983310A (en) * | 1997-02-13 | 1999-11-09 | Novell, Inc. | Pin management of accelerator for interpretive environments |
US5974505A (en) * | 1997-09-02 | 1999-10-26 | International Business Machines Corporation | Method and system for reducing power consumption of a non-blocking cache within a data processing system |
JPH11184752A (ja) | 1997-12-19 | 1999-07-09 | Hitachi Ltd | データ処理装置及びデータ処理システム |
US6138208A (en) * | 1998-04-13 | 2000-10-24 | International Business Machines Corporation | Multiple level cache memory with overlapped L1 and L2 memory access |
JP3439350B2 (ja) * | 1998-10-02 | 2003-08-25 | Necエレクトロニクス株式会社 | キャッシュ・メモリ制御方法及びキャッシュ・メモリ制御装置 |
US6449694B1 (en) * | 1999-07-27 | 2002-09-10 | Intel Corporation | Low power cache operation through the use of partial tag comparison |
US6356990B1 (en) * | 2000-02-02 | 2002-03-12 | International Business Machines Corporation | Set-associative cache memory having a built-in set prediction array |
US6549986B1 (en) * | 2000-06-20 | 2003-04-15 | Conexant Systems, Inc. | Low power instruction cache |
US6535959B1 (en) * | 2000-09-05 | 2003-03-18 | Conexant Systems, Inc. | Circuit and method for reducing power consumption in an instruction cache |
-
2000
- 2000-12-22 JP JP2000391369A patent/JP2002196981A/ja active Pending
-
2001
- 2001-12-20 TW TW090131653A patent/TW581966B/zh not_active IP Right Cessation
- 2001-12-21 DE DE60127520T patent/DE60127520T2/de not_active Expired - Fee Related
- 2001-12-21 CN CNB011457651A patent/CN1155893C/zh not_active Expired - Fee Related
- 2001-12-21 EP EP01310811A patent/EP1217502B1/de not_active Expired - Lifetime
- 2001-12-21 KR KR1020010082560A patent/KR100758185B1/ko not_active IP Right Cessation
- 2001-12-21 US US10/023,905 patent/US6760810B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR100758185B1 (ko) | 2007-09-13 |
JP2002196981A (ja) | 2002-07-12 |
CN1367428A (zh) | 2002-09-04 |
EP1217502A1 (de) | 2002-06-26 |
US20020080662A1 (en) | 2002-06-27 |
CN1155893C (zh) | 2004-06-30 |
TW581966B (en) | 2004-04-01 |
EP1217502B1 (de) | 2007-03-28 |
DE60127520T2 (de) | 2007-09-06 |
US6760810B2 (en) | 2004-07-06 |
KR20020051874A (ko) | 2002-06-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |