DE60138857D1 - Multiport-Cachespeicher - Google Patents
Multiport-CachespeicherInfo
- Publication number
- DE60138857D1 DE60138857D1 DE60138857T DE60138857T DE60138857D1 DE 60138857 D1 DE60138857 D1 DE 60138857D1 DE 60138857 T DE60138857 T DE 60138857T DE 60138857 T DE60138857 T DE 60138857T DE 60138857 D1 DE60138857 D1 DE 60138857D1
- Authority
- DE
- Germany
- Prior art keywords
- multiport cache
- multiport
- cache
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0853—Cache with multiport tag or data arrays
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000244524A JP2002055879A (ja) | 2000-08-11 | 2000-08-11 | マルチポートキャッシュメモリ |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60138857D1 true DE60138857D1 (de) | 2009-07-16 |
Family
ID=18735207
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60138857T Expired - Lifetime DE60138857D1 (de) | 2000-08-11 | 2001-08-03 | Multiport-Cachespeicher |
Country Status (6)
Country | Link |
---|---|
US (1) | US6845429B2 (de) |
EP (1) | EP1179778B1 (de) |
JP (1) | JP2002055879A (de) |
KR (1) | KR100397413B1 (de) |
DE (1) | DE60138857D1 (de) |
TW (1) | TW508801B (de) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020103974A1 (en) * | 2000-11-29 | 2002-08-01 | Giacomini Peter Joseph | Method and apparatus for economical cache population |
EP1512078B1 (de) * | 2002-05-24 | 2012-04-11 | Silicon Hive B.V. | Programmierbare zugriffslatenzzeit in einem pseudo-multiportspeicher |
JP3784766B2 (ja) | 2002-11-01 | 2006-06-14 | 株式会社半導体理工学研究センター | 多ポート統合キャッシュ |
JP2008542945A (ja) * | 2005-06-09 | 2008-11-27 | エヌエックスピー ビー ヴィ | マルチポートキャッシュメモリのアーキテクチャ |
US8429319B2 (en) * | 2005-09-28 | 2013-04-23 | Hynix Semiconductor Inc. | Multi-port memory device with serial input/output interface |
KR100721581B1 (ko) * | 2005-09-29 | 2007-05-23 | 주식회사 하이닉스반도체 | 직렬 입/출력 인터페이스를 가진 멀티 포트 메모리 소자 |
DE102006045248A1 (de) * | 2005-09-29 | 2007-04-19 | Hynix Semiconductor Inc., Ichon | Multiport-Speichervorrichtung mit serieller Eingabe-/Ausgabeschnittstelle |
KR100695436B1 (ko) * | 2006-04-13 | 2007-03-16 | 주식회사 하이닉스반도체 | 직렬 입/출력 인터페이스를 가진 멀티 포트 메모리 소자 및그의 동작 모드 제어방법 |
KR100695437B1 (ko) * | 2006-04-13 | 2007-03-16 | 주식회사 하이닉스반도체 | 멀티 포트 메모리 소자 |
KR100695435B1 (ko) * | 2006-04-13 | 2007-03-16 | 주식회사 하이닉스반도체 | 반도체 메모리 소자 |
JP2008009591A (ja) * | 2006-06-28 | 2008-01-17 | Matsushita Electric Ind Co Ltd | キャッシュメモリシステム |
US8370557B2 (en) * | 2008-12-19 | 2013-02-05 | Intel Corporation | Pseudo dual-port SRAM and a shared memory switch using multiple memory banks and a sideband memory |
KR101788245B1 (ko) | 2011-02-25 | 2017-11-16 | 삼성전자주식회사 | 다중 포트 캐시 메모리 장치 및 그 구동 방법 |
US8843690B2 (en) | 2011-07-11 | 2014-09-23 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Memory conflicts learning capability |
EP3188025A1 (de) * | 2015-12-29 | 2017-07-05 | Teknologian Tutkimuskeskus VTT Oy | Speicherknoten mit zwischenspeicher für computer mit emuliertem gemeinsamem speicher |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4153735A (en) | 1977-11-01 | 1979-05-08 | Uniscope, Inc. | Lubricant-binder additive for densifying animal feed material |
US4905188A (en) * | 1988-02-22 | 1990-02-27 | International Business Machines Corporation | Functional cache memory chip architecture for improved cache access |
EP0439952A3 (en) * | 1990-01-31 | 1992-09-09 | Sgs-Thomson Microelectronics, Inc. | Dual-port cache tag memory |
JP2822588B2 (ja) * | 1990-04-30 | 1998-11-11 | 日本電気株式会社 | キャッシュメモリ装置 |
EP0553743A1 (de) * | 1992-01-31 | 1993-08-04 | Motorola, Inc. | Cachespeichersteuerungseinrichtung |
JPH0836525A (ja) | 1994-07-21 | 1996-02-06 | Hitachi Ltd | 多重アクセスキャッシュ記憶装置 |
US5761714A (en) * | 1996-04-26 | 1998-06-02 | International Business Machines Corporation | Single-cycle multi-accessible interleaved cache |
JP3068469B2 (ja) * | 1996-08-28 | 2000-07-24 | 新潟日本電気株式会社 | 2次レベルキャッシュメモリシステム |
US6047358A (en) * | 1997-10-31 | 2000-04-04 | Philips Electronics North America Corporation | Computer system, cache memory and process for cache entry replacement with selective locking of elements in different ways and groups |
KR19990057856A (ko) * | 1997-12-30 | 1999-07-15 | 김영환 | 저전력 캐쉬 메모리 장치 |
JP2000276400A (ja) | 1999-03-25 | 2000-10-06 | Univ Hiroshima | アドレス及びデータ転送回路 |
KR100395768B1 (ko) * | 2001-06-16 | 2003-08-21 | 삼성전자주식회사 | 멀티 레벨 캐쉬 시스템 |
-
2000
- 2000-08-11 JP JP2000244524A patent/JP2002055879A/ja active Pending
-
2001
- 2001-08-02 US US09/919,859 patent/US6845429B2/en not_active Expired - Lifetime
- 2001-08-03 EP EP01118905A patent/EP1179778B1/de not_active Expired - Lifetime
- 2001-08-03 DE DE60138857T patent/DE60138857D1/de not_active Expired - Lifetime
- 2001-08-08 TW TW090119391A patent/TW508801B/zh not_active IP Right Cessation
- 2001-08-10 KR KR10-2001-0048243A patent/KR100397413B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
JP2002055879A (ja) | 2002-02-20 |
TW508801B (en) | 2002-11-01 |
EP1179778A2 (de) | 2002-02-13 |
US6845429B2 (en) | 2005-01-18 |
KR100397413B1 (ko) | 2003-09-13 |
US20020019912A1 (en) | 2002-02-14 |
EP1179778A3 (de) | 2007-08-01 |
KR20020013772A (ko) | 2002-02-21 |
EP1179778B1 (de) | 2009-06-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |