DE60124665D1 - Herstellungsverfahren für eine leiterplatte - Google Patents

Herstellungsverfahren für eine leiterplatte

Info

Publication number
DE60124665D1
DE60124665D1 DE60124665T DE60124665T DE60124665D1 DE 60124665 D1 DE60124665 D1 DE 60124665D1 DE 60124665 T DE60124665 T DE 60124665T DE 60124665 T DE60124665 T DE 60124665T DE 60124665 D1 DE60124665 D1 DE 60124665D1
Authority
DE
Germany
Prior art keywords
pcb
manufacturing process
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60124665T
Other languages
English (en)
Other versions
DE60124665T2 (de
Inventor
Eiji Kawamoto
Shigeru Yamane
Toshiaki Takenaka
Toshihiro Nishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE60124665D1 publication Critical patent/DE60124665D1/de
Publication of DE60124665T2 publication Critical patent/DE60124665T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0191—Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
DE60124665T 2000-06-05 2001-06-05 Herstellungsverfahren für eine leiterplatte Expired - Lifetime DE60124665T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2000167263A JP4147723B2 (ja) 2000-06-05 2000-06-05 プリント配線板
JP2000167263 2000-06-05
PCT/JP2001/004754 WO2001095678A1 (fr) 2000-06-05 2001-06-05 Procede de fabrication de carte a circuit imprime

Publications (2)

Publication Number Publication Date
DE60124665D1 true DE60124665D1 (de) 2007-01-04
DE60124665T2 DE60124665T2 (de) 2007-03-08

Family

ID=18670441

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60124665T Expired - Lifetime DE60124665T2 (de) 2000-06-05 2001-06-05 Herstellungsverfahren für eine leiterplatte

Country Status (6)

Country Link
US (1) US6890449B2 (de)
EP (1) EP1229770B1 (de)
JP (1) JP4147723B2 (de)
CN (1) CN1235451C (de)
DE (1) DE60124665T2 (de)
WO (1) WO2001095678A1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6465084B1 (en) * 2001-04-12 2002-10-15 International Business Machines Corporation Method and structure for producing Z-axis interconnection assembly of printed wiring board elements
JP2004095242A (ja) * 2002-08-30 2004-03-25 Tsubame Musen Kk ロータリーエンコーダ及びその基板製造方法
US7830367B2 (en) * 2004-05-21 2010-11-09 Nissha Printing Co., Ltd. Touch panel and protective panel for display window of electronic device using the same
US7485967B2 (en) * 2005-03-10 2009-02-03 Sanyo Electric Co., Ltd. Semiconductor device with via hole for electric connection
JP5214154B2 (ja) * 2007-01-19 2013-06-19 住友電気工業株式会社 プリント配線板およびその製造方法
JP5874343B2 (ja) 2011-11-18 2016-03-02 富士通株式会社 積層回路基板の製造方法、積層回路基板、および電子機器
JP2014116428A (ja) * 2012-12-07 2014-06-26 Sumitomo Electric Printed Circuit Inc 多層プリント配線板及びその製造方法
CN107072041B (zh) * 2017-04-25 2019-10-11 安徽宏鑫电子科技有限公司 一种双面pcb
CN114449771B (zh) * 2021-09-27 2024-02-13 深圳市百柔新材料技术有限公司 一种双面过孔陶瓷覆铜板的制备方法及电路板
CN114401586B (zh) * 2022-02-08 2024-01-30 深圳市顺新安电子有限公司 一种smt模板的制备方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01281795A (ja) * 1988-05-07 1989-11-13 Fujitsu Ltd セラミック基板の製造方法
US5067859A (en) * 1990-02-15 1991-11-26 Systems Division Incorporated Method for drilling small holes in printed circuit boards
JP2601128B2 (ja) 1992-05-06 1997-04-16 松下電器産業株式会社 回路形成用基板の製造方法および回路形成用基板
JP3311899B2 (ja) 1995-01-20 2002-08-05 松下電器産業株式会社 回路基板及びその製造方法
JP3935523B2 (ja) * 1996-03-06 2007-06-27 松下電器産業株式会社 プリント配線板の製造方法
JP3738536B2 (ja) * 1997-08-28 2006-01-25 松下電器産業株式会社 プリント配線基板の製造方法
JPH11298105A (ja) * 1998-04-07 1999-10-29 Asahi Chem Ind Co Ltd ビアホール充填型プリント基板およびその製造方法

Also Published As

Publication number Publication date
US20020170876A1 (en) 2002-11-21
US6890449B2 (en) 2005-05-10
DE60124665T2 (de) 2007-03-08
WO2001095678A1 (fr) 2001-12-13
JP2001352138A (ja) 2001-12-21
CN1383707A (zh) 2002-12-04
EP1229770A4 (de) 2004-09-29
EP1229770A1 (de) 2002-08-07
JP4147723B2 (ja) 2008-09-10
CN1235451C (zh) 2006-01-04
EP1229770B1 (de) 2006-11-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP

8320 Willingness to grant licences declared (paragraph 23)