DE60117102D1 - Pegelumsetzer - Google Patents
PegelumsetzerInfo
- Publication number
- DE60117102D1 DE60117102D1 DE60117102T DE60117102T DE60117102D1 DE 60117102 D1 DE60117102 D1 DE 60117102D1 DE 60117102 T DE60117102 T DE 60117102T DE 60117102 T DE60117102 T DE 60117102T DE 60117102 D1 DE60117102 D1 DE 60117102D1
- Authority
- DE
- Germany
- Prior art keywords
- level converter
- converter
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000086385A JP3699878B2 (ja) | 2000-03-27 | 2000-03-27 | 半導体集積回路 |
JP2000086385 | 2000-03-27 | ||
JP2000325047A JP3667622B2 (ja) | 2000-10-25 | 2000-10-25 | レベル変換回路及び半導体集積回路 |
JP2000325047 | 2000-10-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60117102D1 true DE60117102D1 (de) | 2006-04-20 |
DE60117102T2 DE60117102T2 (de) | 2006-08-10 |
Family
ID=26588413
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60117102T Expired - Lifetime DE60117102T2 (de) | 2000-03-27 | 2001-03-13 | Pegelumsetzer |
Country Status (4)
Country | Link |
---|---|
US (1) | US6466054B2 (de) |
EP (1) | EP1139567B1 (de) |
KR (1) | KR100466581B1 (de) |
DE (1) | DE60117102T2 (de) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3865689B2 (ja) * | 2002-01-15 | 2007-01-10 | 松下電器産業株式会社 | レベルシフト回路 |
US6683486B2 (en) * | 2002-04-02 | 2004-01-27 | Infineon Technologies Ag | Low voltage shifter with latching function |
US6650167B1 (en) * | 2002-06-06 | 2003-11-18 | Broadcom Corporation | Multi-level/single ended input level shifter circuit |
DE10230168B9 (de) * | 2002-07-04 | 2004-09-16 | Infineon Technologies Ag | Pegelumsetz-Einrichtung |
JP3833199B2 (ja) * | 2003-07-24 | 2006-10-11 | 沖電気工業株式会社 | 相補信号発生回路 |
US6944843B2 (en) * | 2003-08-05 | 2005-09-13 | Bae Systems, Information And Electronic Systems Integration, Inc. | Method for providing a cell-based ASIC device with multiple power supply voltages |
JP4230881B2 (ja) * | 2003-10-23 | 2009-02-25 | 富士通マイクロエレクトロニクス株式会社 | 半導体集積回路、及びレベル変換回路 |
US7345510B1 (en) * | 2006-08-31 | 2008-03-18 | Ati Technologies Inc. | Method and apparatus for generating a reference signal and generating a scaled output signal based on an input signal |
TW200849820A (en) * | 2007-06-05 | 2008-12-16 | Holtek Semiconductor Inc | Integrated circuit with plural level shifters |
US7560970B2 (en) | 2007-08-08 | 2009-07-14 | Freescale Semiconductor, Inc. | Level shifter |
US9312860B1 (en) * | 2015-02-26 | 2016-04-12 | International Business Machines Corporation | Gated differential logic circuit |
JP6952619B2 (ja) * | 2018-02-21 | 2021-10-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP7395390B2 (ja) | 2020-03-10 | 2023-12-11 | 株式会社東芝 | 半導体装置 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3967252A (en) * | 1974-10-03 | 1976-06-29 | Mostek Corporation | Sense AMP for random access memory |
JPS51139220A (en) * | 1975-05-28 | 1976-12-01 | Hitachi Ltd | Sense amplifier |
JP2877369B2 (ja) * | 1989-09-11 | 1999-03-31 | 株式会社東芝 | デマルチプレクサ |
US5157281A (en) * | 1991-07-12 | 1992-10-20 | Texas Instruments Incorporated | Level-shifter circuit for integrated circuits |
US5204557A (en) * | 1991-10-15 | 1993-04-20 | National Semiconductor Corporation | Digital signal level translator |
JPH08330939A (ja) * | 1995-06-05 | 1996-12-13 | Toshiba Microelectron Corp | レベルシフタ回路 |
JP3123463B2 (ja) * | 1997-05-16 | 2001-01-09 | 日本電気株式会社 | レベル変換回路 |
JP3731322B2 (ja) * | 1997-11-04 | 2006-01-05 | ソニー株式会社 | レベルシフト回路 |
-
2001
- 2001-03-13 DE DE60117102T patent/DE60117102T2/de not_active Expired - Lifetime
- 2001-03-13 EP EP01302308A patent/EP1139567B1/de not_active Expired - Lifetime
- 2001-03-20 US US09/811,699 patent/US6466054B2/en not_active Expired - Fee Related
- 2001-03-23 KR KR10-2001-0015136A patent/KR100466581B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US6466054B2 (en) | 2002-10-15 |
US20010024130A1 (en) | 2001-09-27 |
KR20010090732A (ko) | 2001-10-19 |
EP1139567A1 (de) | 2001-10-04 |
DE60117102T2 (de) | 2006-08-10 |
KR100466581B1 (ko) | 2005-01-15 |
EP1139567B1 (de) | 2006-02-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |