DE60116060D1 - Rekonfigurierbare logik für einen rechner - Google Patents

Rekonfigurierbare logik für einen rechner

Info

Publication number
DE60116060D1
DE60116060D1 DE60116060T DE60116060T DE60116060D1 DE 60116060 D1 DE60116060 D1 DE 60116060D1 DE 60116060 T DE60116060 T DE 60116060T DE 60116060 T DE60116060 T DE 60116060T DE 60116060 D1 DE60116060 D1 DE 60116060D1
Authority
DE
Germany
Prior art keywords
logic
memory
interface
programmable logic
interface information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60116060T
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English (en)
Other versions
DE60116060T2 (de
Inventor
John Morelli
Richard Kendall
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE60116060D1 publication Critical patent/DE60116060D1/de
Application granted granted Critical
Publication of DE60116060T2 publication Critical patent/DE60116060T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Hardware Redundancy (AREA)
DE60116060T 2000-02-15 2001-02-14 Rekonfigurierbare logik für einen rechner Expired - Lifetime DE60116060T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US505059 2000-02-15
US09/505,059 US6438737B1 (en) 2000-02-15 2000-02-15 Reconfigurable logic for a computer
PCT/US2001/004733 WO2001061525A2 (en) 2000-02-15 2001-02-14 Reconfigurable logic for a computer

Publications (2)

Publication Number Publication Date
DE60116060D1 true DE60116060D1 (de) 2006-01-26
DE60116060T2 DE60116060T2 (de) 2006-07-13

Family

ID=24008825

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60116060T Expired - Lifetime DE60116060T2 (de) 2000-02-15 2001-02-14 Rekonfigurierbare logik für einen rechner

Country Status (8)

Country Link
US (1) US6438737B1 (de)
EP (2) EP1536346A3 (de)
JP (1) JP4510353B2 (de)
AT (1) ATE313829T1 (de)
AU (1) AU2001237005A1 (de)
DE (1) DE60116060T2 (de)
HK (1) HK1048871B (de)
WO (1) WO2001061525A2 (de)

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HK1048871B (zh) 2006-04-28
EP1257928A2 (de) 2002-11-20
US6438737B1 (en) 2002-08-20
AU2001237005A1 (en) 2001-08-27
JP4510353B2 (ja) 2010-07-21
WO2001061525A2 (en) 2001-08-23
HK1048871A1 (en) 2003-04-17
WO2001061525A3 (en) 2002-02-28
DE60116060T2 (de) 2006-07-13
ATE313829T1 (de) 2006-01-15
JP2003524969A (ja) 2003-08-19
EP1536346A3 (de) 2009-04-29
EP1257928B1 (de) 2005-12-21
EP1536346A2 (de) 2005-06-01

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