DE60101117D1 - Anordnung und Verfahren zur Aufrechterhaltung des eingeschwungenen Zustandes eines Phasenregelkreises während eines Taktstopps - Google Patents

Anordnung und Verfahren zur Aufrechterhaltung des eingeschwungenen Zustandes eines Phasenregelkreises während eines Taktstopps

Info

Publication number
DE60101117D1
DE60101117D1 DE60101117T DE60101117T DE60101117D1 DE 60101117 D1 DE60101117 D1 DE 60101117D1 DE 60101117 T DE60101117 T DE 60101117T DE 60101117 T DE60101117 T DE 60101117T DE 60101117 D1 DE60101117 D1 DE 60101117D1
Authority
DE
Germany
Prior art keywords
maintaining
arrangement
steady state
locked loop
phase locked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60101117T
Other languages
English (en)
Other versions
DE60101117T2 (de
Inventor
Edward R Helder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE60101117D1 publication Critical patent/DE60101117D1/de
Publication of DE60101117T2 publication Critical patent/DE60101117T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE60101117T 2000-05-01 2001-04-30 Anordnung und Verfahren zur Aufrechterhaltung des eingeschwungenen Zustandes eines Phasenregelkreises während eines Taktstopps Expired - Lifetime DE60101117T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/562,043 US6625559B1 (en) 2000-05-01 2000-05-01 System and method for maintaining lock of a phase locked loop feedback during clock halt
US562043 2000-05-01

Publications (2)

Publication Number Publication Date
DE60101117D1 true DE60101117D1 (de) 2003-12-11
DE60101117T2 DE60101117T2 (de) 2004-08-26

Family

ID=24244548

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60101117T Expired - Lifetime DE60101117T2 (de) 2000-05-01 2001-04-30 Anordnung und Verfahren zur Aufrechterhaltung des eingeschwungenen Zustandes eines Phasenregelkreises während eines Taktstopps

Country Status (4)

Country Link
US (1) US6625559B1 (de)
EP (1) EP1152536B1 (de)
JP (1) JP4430836B2 (de)
DE (1) DE60101117T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6920572B2 (en) * 2000-11-15 2005-07-19 Texas Instruments Incorporated Unanimous voting for disabling of shared component clocking in a multicore DSP device
US6751743B1 (en) * 2000-12-22 2004-06-15 Cisco Technology, Inc. Method and apparatus for selecting a first clock and second clock for first and second devices respectively from an up-converted clock and an aligned clock for synchronization
US6810486B2 (en) * 2001-03-28 2004-10-26 Intel Corporation Method and apparatus for de-skewing a clock using a first and second phase locked loop and a clock tree
US6934898B1 (en) * 2001-11-30 2005-08-23 Koninklijke Philips Electronics N.V. Test circuit topology reconfiguration and utilization techniques
US6647081B2 (en) * 2001-12-12 2003-11-11 Emulex Corporation Phase-locked loop (PLL) circuit for selectively correcting clock skew in different modes
JP2007193751A (ja) * 2006-01-23 2007-08-02 Nec Electronics Corp 半導体装置およびデータ入出力システム
KR100791002B1 (ko) 2006-11-15 2008-01-03 삼성전자주식회사 락킹 범위를 극대화시키며 번-인 테스트할 수 있는 위상동기 회로 및 그 번-인 테스트 방법
US7856562B2 (en) * 2007-05-02 2010-12-21 Advanced Micro Devices, Inc. Selective deactivation of processor cores in multiple processor core systems
US20080313478A1 (en) * 2007-06-15 2008-12-18 Wong Kar Leong Mechanism to gate clock trunk and shut down clock source
CN102971638B (zh) 2010-07-07 2015-08-19 株式会社爱德万测试 对半导体器件进行试验的试验装置及试验方法
US8994458B2 (en) 2011-11-08 2015-03-31 Qualcomm Incorporated Oscillator based frequency locked loop
US20180311139A1 (en) 2017-04-28 2018-11-01 L'oreal Hair-treatment compositions comprising a polyurethane latex polymer and cationic compound
CN116521613B (zh) * 2023-07-04 2023-08-25 南京启见半导体科技有限公司 超低延迟的时钟域切换数据传输系统

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4876446A (en) 1987-02-06 1989-10-24 Matsushita Electric Works, Ltd. Optical sensor with optical interconnection board
US5349587A (en) * 1992-03-26 1994-09-20 Northern Telecom Limited Multiple clock rate test apparatus for testing digital systems
US5517147A (en) 1994-11-17 1996-05-14 Unisys Corporation Multiple-phase clock signal generator for integrated circuits, comprising PLL, counter, and logic circuits
US5864564A (en) 1995-11-17 1999-01-26 Sun Microsystems, Inc. Control circuit for deterministic stopping of an integrated circuit internal clock
US5900757A (en) 1996-05-01 1999-05-04 Sun Microsystems, Inc. Clock stopping schemes for data buffer
CA2226061C (en) * 1997-12-31 2002-05-28 Logicvision, Inc. Method and apparatus for controlling power level during bist

Also Published As

Publication number Publication date
DE60101117T2 (de) 2004-08-26
EP1152536A1 (de) 2001-11-07
EP1152536B1 (de) 2003-11-05
JP4430836B2 (ja) 2010-03-10
US6625559B1 (en) 2003-09-23
JP2002032144A (ja) 2002-01-31

Similar Documents

Publication Publication Date Title
DE60101117D1 (de) Anordnung und Verfahren zur Aufrechterhaltung des eingeschwungenen Zustandes eines Phasenregelkreises während eines Taktstopps
DE60217767D1 (de) Verfahren und Vorrichtung zum Gewährleisten der Verriegelung einer Verzögerungsregelschleife auf einer Tiefstverzögerung
DE60122970D1 (de) Frequenzsynthesizer mit gebrochenem Teilverhältnis und Verfahren zur Phasenfehlerunterdrückung dafür
DE60121400D1 (de) Verfahren zur Geräuschreduzierung einer Turbomaschine mittels Phasenverschiebung/-auslöschung und Vorrichtung zur Ausführung des Verfahrens
DE19882493T1 (de) Verfahren zur Verflüssigung eines Erdgasstroms, enthaltend mindestens eine einfrierbare Komponente
DE50113959D1 (de) Projektionssystem und Verfahren zum Betreiben eines Projektionssystems
DE10196629T1 (de) Sensorsystem für ein angetriebenes Schließsystem und Verfahren zum bedarfsweisen Verhindern des Schließens eines angetriebenen Schließsystems
DE60021055D1 (de) Gefaltetes filterelement und verfahren zur herstellung eines gefalteten filterelements
DE60230791D1 (de) Verfahren und vorrichtung zur vermeidung des pumpens in einer gasturbine
DE60008179D1 (de) Verfahren zur Änderung der Länge eines kohärenten Gasstrahls
DE60140591D1 (de) System und Verfahren zum Starten eines Stromerzeugungsaggregates mit Mikroturbine
HUP0204088A3 (en) Method for removal of nox and n2o
DE69503859D1 (de) Verfahren und Schaltung zur Steuerung eines Phasenregelkreises
DE60006713D1 (de) Verfahren zum steuern des wachstums eines halbleiterkristalls
DE60032848D1 (de) Verfahren und Vorrichtung zur Phasenkorrektur
DE60125299D1 (de) Frequenzsynthesizer und Verfahren zur Frequenzsynthese mit geringem Rauschen
DE602004005912D1 (de) Vorrichtung und Verfahren zur Reduzierung der Verriegelungszeit einer Phasenregelschleife
DE50109107D1 (de) Anordnung und verfahren zum kühlen
DE60112995D1 (de) Verfahren und Anordnung zur Steuerung der Phase von vier Signalen wechselseitig in Quadratur
DE102005050621A8 (de) Phasenregelkreis und Verfahren zum Betrieb eines Phasenregelkreises
DE50115385D1 (de) Doppelseitiges klebeband und verfahren zur befestigung eines dichtungselements an einer verwendungsstelle
DE10393732D2 (de) Phasenregelkreis mit Pulsgenerator und Verfahren zum Betrieb des Phasenregelkreises
DE60104574D1 (de) Verfahren und Vorrichtung zur Herstellung eines faserverstärkten Teils
ATE292713T1 (de) Verfahren und maschine zur unterstopfung eines gleises
DE60108295D1 (de) Verfahren zum Reglung der Charakteristiken eines spannungsgesteuerten Oszillators

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE