DE60008139D1 - Cachespeicheranordnung für einen digitalen signalprozessor - Google Patents

Cachespeicheranordnung für einen digitalen signalprozessor

Info

Publication number
DE60008139D1
DE60008139D1 DE60008139T DE60008139T DE60008139D1 DE 60008139 D1 DE60008139 D1 DE 60008139D1 DE 60008139 T DE60008139 T DE 60008139T DE 60008139 T DE60008139 T DE 60008139T DE 60008139 D1 DE60008139 D1 DE 60008139D1
Authority
DE
Germany
Prior art keywords
digital signal
signal processor
storage arrangement
cache storage
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60008139T
Other languages
English (en)
Other versions
DE60008139T2 (de
Inventor
D Krivacek
Joern Soerensen
Frederic Boutaud
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Application granted granted Critical
Publication of DE60008139D1 publication Critical patent/DE60008139D1/de
Publication of DE60008139T2 publication Critical patent/DE60008139T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G06F15/7846—On-chip cache and off-chip main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W74/00—Wireless channel access
    • H04W74/04—Scheduled access

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)
DE2000608139 1999-11-05 2000-11-06 Cachespeicheranordnung für einen digitalen signalprozessor Expired - Lifetime DE60008139T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16381699P 1999-11-05 1999-11-05
US163816P 1999-11-05
PCT/US2000/030454 WO2001035246A2 (en) 1999-11-05 2000-11-06 Cache memory system and method for a digital signal processor

Publications (2)

Publication Number Publication Date
DE60008139D1 true DE60008139D1 (de) 2004-03-11
DE60008139T2 DE60008139T2 (de) 2004-11-18

Family

ID=22591705

Family Applications (3)

Application Number Title Priority Date Filing Date
DE60027748T Expired - Lifetime DE60027748T2 (de) 1999-11-05 2000-11-03 Busarchitektur und verteiltes busarbitrierungsverfahren für einen kommunikationsprozessor
DE60017775T Expired - Lifetime DE60017775T2 (de) 1999-11-05 2000-11-03 Architektur und system von einem generischen und seriellen port
DE2000608139 Expired - Lifetime DE60008139T2 (de) 1999-11-05 2000-11-06 Cachespeicheranordnung für einen digitalen signalprozessor

Family Applications Before (2)

Application Number Title Priority Date Filing Date
DE60027748T Expired - Lifetime DE60027748T2 (de) 1999-11-05 2000-11-03 Busarchitektur und verteiltes busarbitrierungsverfahren für einen kommunikationsprozessor
DE60017775T Expired - Lifetime DE60017775T2 (de) 1999-11-05 2000-11-03 Architektur und system von einem generischen und seriellen port

Country Status (5)

Country Link
EP (3) EP1226505B1 (de)
CN (3) CN100353349C (de)
AU (3) AU1458501A (de)
DE (3) DE60027748T2 (de)
WO (3) WO2001035210A2 (de)

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KR100532416B1 (ko) * 2003-01-18 2005-11-30 삼성전자주식회사 다중 소스의 다중 채널로의 할당 방법 및 시스템
KR100463205B1 (ko) * 2003-02-13 2004-12-23 삼성전자주식회사 시퀀셜 버퍼를 내장하여 디에스피의 데이터 억세스 성능을향상시키는 컴퓨터 시스템 및 그 컴퓨터 시스템의 데이터억세스 방법
US20050154928A1 (en) * 2004-01-08 2005-07-14 International Business Machines Corporation Remote power-on functionality in a partitioned environment
CN1661576B (zh) * 2004-02-25 2010-04-28 中国科学院计算技术研究所 Soc架构下的高速总线动态变频装置和处理器核接口
US7957428B2 (en) * 2004-05-21 2011-06-07 Intel Corporation Methods and apparatuses to effect a variable-width link
CN100389413C (zh) * 2004-09-15 2008-05-21 北京中星微电子有限公司 串行通信总线外部设备接口
CN100388251C (zh) * 2004-12-24 2008-05-14 刘龙威 外部数据存储设备共享切换电路及其应用系统
US7348799B2 (en) * 2005-01-11 2008-03-25 Hewlett-Packard Development Company, L.P. System and method for generating a trigger signal
US7428603B2 (en) 2005-06-30 2008-09-23 Sigmatel, Inc. System and method for communicating with memory devices via plurality of state machines and a DMA controller
JP4747896B2 (ja) * 2006-03-17 2011-08-17 ソニー株式会社 情報処理装置および方法、並びにプログラム
US7930576B2 (en) * 2007-04-10 2011-04-19 Standard Microsystems Corporation Sharing non-sharable devices between an embedded controller and a processor in a computer system
CN101840385B (zh) * 2009-03-19 2012-07-18 承景科技股份有限公司 数据存取系统
CN102654853B (zh) * 2011-03-04 2015-03-04 上海华虹集成电路有限责任公司 一种采用两个微处理器的Nandflash控制器
CN102662911A (zh) * 2012-03-19 2012-09-12 中国科学院上海技术物理研究所 一种板级重构红外信号处理机的控制方法
US9129072B2 (en) * 2012-10-15 2015-09-08 Qualcomm Incorporated Virtual GPIO
US9946675B2 (en) * 2013-03-13 2018-04-17 Atieva, Inc. Fault-tolerant loop for a communication bus
CN104216857B (zh) * 2013-05-31 2017-09-22 英业达科技有限公司 多工切换装置及其切换方法
FR3026869B1 (fr) * 2014-10-07 2016-10-28 Sagem Defense Securite Systeme embarque sur puce a haute surete de fonctionnement
US9450582B2 (en) 2015-02-03 2016-09-20 Freescale Semiconductor, Inc. Programmable buffer system
EP4145297A1 (de) * 2016-01-22 2023-03-08 Sony Interactive Entertainment Inc. Simulation des verhaltens eines altbusses für rückwärtskompatibilität
GB2553338B (en) * 2016-09-02 2019-11-20 Advanced Risc Mach Ltd Serial communication control
CN106980577B (zh) * 2017-03-20 2020-04-28 华为机器有限公司 输入输出处理方法、装置及终端
US10558604B2 (en) * 2017-12-20 2020-02-11 Qualcomm Incorporated Communication interface transaction security
CN109725250B (zh) * 2019-01-04 2021-07-13 珠海亿智电子科技有限公司 一种片上系统芯片模拟电路的测试系统及测试方法
CN111045980A (zh) * 2019-12-24 2020-04-21 广东嘉泰智能技术有限公司 一种多核处理器
CN114297105B (zh) * 2021-12-29 2024-04-05 合肥市芯海电子科技有限公司 一种直接存储器访问的嵌入式控制电路、芯片和电子设备

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US4831520A (en) * 1987-02-24 1989-05-16 Digital Equipment Corporation Bus interface circuit for digital data processor
EP0426413B1 (de) * 1989-11-03 1997-05-07 Compaq Computer Corporation Multiprozessorarbitrierung in für Einzelprozessor bestimmten Arbitrierungsschemas
DE69430793T2 (de) * 1994-01-27 2003-02-20 Sun Microsystems Inc Asynchrone serielle kommunickationsschaltung
US5628030A (en) * 1994-03-24 1997-05-06 Multi-Tech Systems, Inc. Virtual modem driver apparatus and method
US5598542A (en) * 1994-08-08 1997-01-28 International Business Machines Corporation Method and apparatus for bus arbitration in a multiple bus information handling system using time slot assignment values
WO1996041267A1 (en) * 1995-06-07 1996-12-19 Ast Research, Inc. Delay reduction in transfer of buffered data between two mutually asynchronous buses
US5809091A (en) * 1996-06-04 1998-09-15 Ericsson, Inc. Timing signal generator for digital communication system
US5805844A (en) * 1996-10-07 1998-09-08 Gustin; Jay W. Control circuit for an interface between a PCI bus and a module bus
US5987568A (en) * 1997-01-10 1999-11-16 3Com Corporation Apparatus and method for operably connecting a processor cache and a cache controller to a digital signal processor
DE19713178A1 (de) * 1997-03-27 1998-10-01 Siemens Ag Schaltungsanordnung mit einem Prozessor und einem Datenspeicher
US5974486A (en) * 1997-08-12 1999-10-26 Atmel Corporation Universal serial bus device controller comprising a FIFO associated with a plurality of endpoints and a memory for storing an identifier of a current endpoint
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Also Published As

Publication number Publication date
CN1399743A (zh) 2003-02-26
CN100353349C (zh) 2007-12-05
CN1279472C (zh) 2006-10-11
WO2001035234A9 (en) 2002-05-30
AU1458501A (en) 2001-06-06
CN100336046C (zh) 2007-09-05
EP1226493B1 (de) 2006-05-03
DE60008139T2 (de) 2004-11-18
CN1387645A (zh) 2002-12-25
DE60017775D1 (de) 2005-03-03
CN1387646A (zh) 2002-12-25
DE60017775T2 (de) 2006-01-12
DE60027748T2 (de) 2007-04-05
EP1236122A2 (de) 2002-09-04
EP1226505B1 (de) 2005-01-26
DE60027748D1 (de) 2006-06-08
WO2001035246A2 (en) 2001-05-17
AU1458801A (en) 2001-06-06
WO2001035234A1 (en) 2001-05-17
EP1236122B1 (de) 2004-02-04
WO2001035210A3 (en) 2002-01-17
AU1465001A (en) 2001-06-06
WO2001035210A2 (en) 2001-05-17
WO2001035246A3 (en) 2002-07-11
EP1226505A1 (de) 2002-07-31
EP1226493A2 (de) 2002-07-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: MEDIATEK INC., HSINCHU, TW