DE60004871D1 - Redundante doppelbank-architektur für einen simultanen flash-speicher - Google Patents

Redundante doppelbank-architektur für einen simultanen flash-speicher

Info

Publication number
DE60004871D1
DE60004871D1 DE60004871T DE60004871T DE60004871D1 DE 60004871 D1 DE60004871 D1 DE 60004871D1 DE 60004871 T DE60004871 T DE 60004871T DE 60004871 T DE60004871 T DE 60004871T DE 60004871 D1 DE60004871 D1 DE 60004871D1
Authority
DE
Germany
Prior art keywords
bank
columns
memory cells
redundant
sector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60004871T
Other languages
German (de)
English (en)
Inventor
Yasushi Kasa
Guowei Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Advanced Micro Devices Inc
Original Assignee
Fujitsu Ltd
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Advanced Micro Devices Inc filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE60004871D1 publication Critical patent/DE60004871D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/781—Masking faults in memories by using spares or by reconfiguring using programmable devices combined in a redundant decoder
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/22—Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • Stored Programmes (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE60004871T 1999-10-19 2000-10-09 Redundante doppelbank-architektur für einen simultanen flash-speicher Expired - Lifetime DE60004871D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16035399P 1999-10-19 1999-10-19
US09/632,390 US6397313B1 (en) 1999-10-19 2000-08-04 Redundant dual bank architecture for a simultaneous operation flash memory
PCT/US2000/027911 WO2001029668A1 (en) 1999-10-19 2000-10-09 Redundant dual bank architecture for a simultaneous operation flash memory

Publications (1)

Publication Number Publication Date
DE60004871D1 true DE60004871D1 (de) 2003-10-02

Family

ID=26856820

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60004871T Expired - Lifetime DE60004871D1 (de) 1999-10-19 2000-10-09 Redundante doppelbank-architektur für einen simultanen flash-speicher

Country Status (9)

Country Link
US (1) US6397313B1 (ja)
EP (1) EP1224549B1 (ja)
JP (1) JP2003512690A (ja)
KR (1) KR20030009310A (ja)
CN (1) CN1379878A (ja)
AT (1) ATE248400T1 (ja)
DE (1) DE60004871D1 (ja)
TW (1) TW484055B (ja)
WO (1) WO2001029668A1 (ja)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6714467B2 (en) * 2002-03-19 2004-03-30 Broadcom Corporation Block redundancy implementation in heirarchical RAM's
CA2360897C (en) * 2001-10-31 2011-01-25 Mosaid Technologies Incorporated Column redundancy for content addressable memory
US7016243B1 (en) * 2002-05-10 2006-03-21 Netlogic Microsystems, Inc. Content addressable memory having column redundancy
KR100490084B1 (ko) * 2002-09-12 2005-05-17 삼성전자주식회사 효율적인 리던던시 구제율을 갖는 반도체 메모리 장치
KR100608592B1 (ko) * 2004-01-27 2006-08-03 삼성전자주식회사 플래시 메모리의 데이터 관리 장치 및 방법
US7068555B2 (en) * 2004-02-20 2006-06-27 Spansion Llc Semiconductor memory storage device and a redundancy control method therefor
US7266667B2 (en) * 2004-11-12 2007-09-04 Infineon Technologies Ag Memory access using multiple sets of address/data lines
US7257745B2 (en) * 2005-01-31 2007-08-14 International Business Machines Corporation Array self repair using built-in self test techniques
US7301832B2 (en) * 2005-11-03 2007-11-27 Atmel Corporation Compact column redundancy CAM architecture for concurrent read and write operations in multi-segment memory arrays
US7441102B2 (en) * 2006-02-28 2008-10-21 Freescale Semiconductor, Inc. Integrated circuit with functional state configurable memory and method of configuring functional states of the integrated circuit memory
KR100769772B1 (ko) 2006-09-29 2007-10-23 주식회사 하이닉스반도체 플래시 메모리 장치 및 이를 이용한 소거 방법
US7652905B2 (en) * 2007-01-04 2010-01-26 Macronix International Co., Ltd. Flash memory array architecture
US20100318720A1 (en) * 2009-06-16 2010-12-16 Saranyan Rajagopalan Multi-Bank Non-Volatile Memory System with Satellite File System
US8201020B2 (en) 2009-11-12 2012-06-12 International Business Machines Corporation Method apparatus and system for a redundant and fault tolerant solid state disk
US11119857B2 (en) * 2012-09-18 2021-09-14 Mosys, Inc. Substitute redundant memory
US8464135B2 (en) 2010-07-13 2013-06-11 Sandisk Technologies Inc. Adaptive flash interface
US9069688B2 (en) 2011-04-15 2015-06-30 Sandisk Technologies Inc. Dynamic optimization of back-end memory system interface
CN102157206A (zh) * 2011-01-17 2011-08-17 上海宏力半导体制造有限公司 具有冗余电路的存储器以及为存储器提供冗余电路的方法
KR102060788B1 (ko) 2012-12-31 2019-12-31 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
US9141291B2 (en) 2013-11-26 2015-09-22 Sandisk Technologies Inc. Adaptive context disbursement for improved performance in non-volatile memory systems
US9384128B2 (en) 2014-04-18 2016-07-05 SanDisk Technologies, Inc. Multi-level redundancy code for non-volatile memory controller
KR20170034177A (ko) * 2015-09-18 2017-03-28 에스케이하이닉스 주식회사 리페어 장치
US10141065B1 (en) * 2017-08-29 2018-11-27 Cypress Semiconductor Corporation Row redundancy with distributed sectors
US11455221B2 (en) * 2019-10-31 2022-09-27 Qualcomm Incorporated Memory with concurrent fault detection and redundancy
WO2022198494A1 (en) 2021-03-24 2022-09-29 Yangtze Memory Technologies Co., Ltd. Memory device with failed main bank repair using redundant bank
WO2022198491A1 (en) * 2021-03-24 2022-09-29 Yangtze Memory Technologies Co., Ltd. Memory device with failed main bank repair using redundant bank

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5349558A (en) 1993-08-26 1994-09-20 Advanced Micro Devices, Inc. Sector-based redundancy architecture
JP3059076B2 (ja) 1995-06-19 2000-07-04 シャープ株式会社 不揮発性半導体記憶装置
KR0172745B1 (ko) 1995-12-29 1999-03-30 김주용 플래쉬 메모리 장치
EP0797145B1 (en) 1996-03-22 2002-06-12 STMicroelectronics S.r.l. Sectorized electrically erasable and programmable non-volatile memory device with redundancy
US5867430A (en) 1996-12-20 1999-02-02 Advanced Micro Devices Inc Bank architecture for a non-volatile memory enabling simultaneous reading and writing
US5847998A (en) 1996-12-20 1998-12-08 Advanced Micro Devices, Inc. Non-volatile memory array that enables simultaneous read and write operations
US6144591A (en) * 1997-12-30 2000-11-07 Mosaid Technologies Incorporated Redundancy selection circuit for semiconductor memories
US6005803A (en) 1998-09-23 1999-12-21 Advanced Micro Devices, Inc. Memory address decoding circuit for a simultaneous operation flash memory device with a flexible bank partition architecture
JP2000235800A (ja) * 1999-02-12 2000-08-29 Mitsubishi Electric Corp 半導体記憶装置
US6144593A (en) * 1999-09-01 2000-11-07 Micron Technology, Inc. Circuit and method for a multiplexed redundancy scheme in a memory device

Also Published As

Publication number Publication date
US6397313B1 (en) 2002-05-28
EP1224549B1 (en) 2003-08-27
KR20030009310A (ko) 2003-01-29
TW484055B (en) 2002-04-21
JP2003512690A (ja) 2003-04-02
ATE248400T1 (de) 2003-09-15
EP1224549A1 (en) 2002-07-24
CN1379878A (zh) 2002-11-13
WO2001029668A1 (en) 2001-04-26

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